Synaptic Transistor Gate Structure for Short- and Long-Term Memory
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Solution Overview
Problem
Existing synaptic devices, such as memristors, face challenges in simultaneously performing signal processing and learning due to difficulties in controlling synaptic strength and maintaining signal direction, leading to limitations in implementing flexible synaptic behavior.
Innovation Solution
A synaptic transistor design with a substrate, expansion gate electrode, gate insulating layer, channel layer, source and drain electrodes, and a pad electrode, utilizing hydrogen ions to adjust threshold voltage and enhance hysteresis, allowing for both short-term and long-term memory characteristics and improved synaptic characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a synaptic transistor is designed to provide both short-term and long-term memory characteristics, then the device functionality and versatility are improved, but the device structure and manufacturing process become more complex
Solution Approach 1:
The patent merges short-term memory and long-term memory functionalities into a single synaptic transistor device. The gate insulating layer simultaneously provides both memory characteristics through its ionic composition and structural properties, eliminating the need for separate memory components and reducing overall device complexity despite the enhanced functionality.
Solution Approach 2:
The gate insulating layer is designed to perform multiple functions: it serves as both the short-term memory medium through ion migration and the long-term memory medium through threshold voltage stabilization. This multi-functional design allows a single component to provide diverse memory characteristics, improving device versatility without proportionally increasing complexity.
2Reliability
If the gate insulating layer thickness is increased to improve retention characteristics for long-term memory, then memory retention is improved, but the threshold voltage increases and hysteresis characteristics deteriorate
Solution Approach 1:
The patent changes the compositional parameters of the gate insulating layer by incorporating specific ionic compounds (such as aluminum oxide with hydrogen ions) that provide both thick-layer retention characteristics and maintained hysteresis. This compositional parameter change allows the device to achieve long-term memory retention without sacrificing threshold voltage control or hysteresis characteristics that would normally deteriorate with increased thickness.
Solution Approach 2:
The gate insulating layer is designed as a composite material structure that combines materials with different properties to achieve both thick-layer retention and proper hysteresis characteristics. The composite structure allows simultaneous optimization of retention characteristics and threshold voltage control, resolving the trade-off between memory retention and manufacturing precision.
3Reliability
If hydrogen ions are used to adjust threshold voltage and induce hysteresis, then synaptic characteristics and signal-to-noise ratio are improved, but the manufacturing process complexity increases
Solution Approach 1:
The gate insulating layer is designed to self-generate and maintain the necessary ionic composition for hysteresis and threshold voltage adjustment. The material inherently contains mobile ions that automatically migrate to create the desired electrical characteristics, eliminating the need for complex post-fabrication ion implantation or charging processes. This self-service approach improves signal-to-noise ratio while keeping manufacturing relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a high signal-to-noise ratio, improved synaptic characteristics, and energy efficiency by inducing hysteresis and adjusting threshold voltage, enabling flexible synaptic behavior and simultaneous short-term and long-term memory operations.
Implementation Method 1
the gate insulating layer including ions, covering the expansion gate electrode
Implementation Method 2
induce a relatively large hysteresis to have a relatively high signal-to-noise ratio
Data Source
AI summary
Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.