Synaptic Weight Control via Memory Cell Array Summation
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Solution Overview
Problem
Current artificial synaptic elements in neuromorphic systems lack reproducibility and control over gradual resistance changes necessary for analog information processing, with existing RRAM and PRAM technologies exhibiting asymmetric and non-reproducible resistance state control.
Innovation Solution
A memory apparatus with a memory array of selectively programmable memory cells connected by bit and word lines, where a controller applies writing and reading voltages to determine synaptic weights by summing currents through selected memory cells, enabling controlled gradual resistance changes and symmetric conductance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If RRAM or PRAM elements are used to implement artificial synaptic elements, then resistance states can be changed, but the resistance control becomes asymmetric and lacks reproducibility
Solution Approach 1:
The patent divides a single synaptic element into multiple memory cells (e.g., 256 memory cells) arranged in a memory array. Each memory cell contributes to the overall conductance, and by controlling the number and state of individual cells, the system achieves fine-grained, reproducible resistance control. This segmentation allows the synaptic weight to be determined by the sum of currents from multiple cells, providing both adaptability and reliability.
2Adaptability or versatility
If digital on/off resistance change is implemented in memory array, then logic states can be stored, but gradual resistance change for analog processing cannot be achieved
Solution Approach 1:
The patent combines multiple digital memory cells to simulate an analog synaptic element. By merging the conductance contributions of 256 individually controllable memory cells, the system creates a unified synaptic weight that can vary gradually. The controller selectively activates specific memory cells within the array, and the summed current from these cells produces a proportional analog-like response, enabling both digital storage reliability and analog processing capability.
3Device complexity
If one memory cell is used as synaptic element, then结构简单 (structure is simple), but controllable and distinguishable gradual current change cannot occur
Solution Approach 1:
The patent transitions from a single-cell structure to a two-dimensional memory array configuration. Instead of relying on a single memory cell with continuous resistance adjustment, the system uses a grid of memory cells (rows and columns) where synaptic weight is determined by selecting and activating specific cells. This dimensional expansion provides precise control over current flow through combinatorial selection of cells, enabling gradual and distinguishable current changes while maintaining structured organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a synaptic element capable of highly linear and reproducible resistance changes, enabling effective synaptic weight determination and analog information processing in neuromorphic systems.
Implementation Method 1
a memory array including a plurality of memory cells capable of selectively storing logic states
Implementation Method 2
determine synaptic weights through a sum of currents flowing through the one or more memory cells
Data Source
AI summary
The present invention provides a memory apparatus capable of causing a gradual resistance change for information processing in an analog manner to a synaptic element for implementing a neuromorphic system. To this end, the present invention provides a memory apparatus including: a memory array including a plurality of memory cells capable of selectively storing logic states and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a writing step and a reading step; a writing unit; and a reading unit, wherein the controller selects, in the writing step, one or more memory cells from among the plurality of memory cells through the writing unit, sequentially applies a writing voltage thereto to allow the logic states to be written therein, and applies, in the reading step, a reading voltage to the one or more memory cells, which are selected to have the logic states written therein, through the reading unit so as to determine synaptic weights through a sum of currents flowing through the one or more memory cells so that the selected one or more memory cells are allowed to be recognized to operate as one synaptic element.The present invention also provides a method for determining a synaptic weight in a memory apparatus including a memory array including a plurality of memory cells capable of selectively storing logic states, bit lines and word lines connected to the plurality of memory cells, the method including: (a) selecting one or more memory cells from among the plurality of memory cells, and sequentially applying a writing voltage to write logic states therein; (b) applying a reading voltage to the one or more memory cells that has been selected to have the logic states written therein; and (c) determining, by the applied reading voltage, a synaptic weight through a sum of currents flowing through the one or more memory cells that has been selected to have the logic states written therein, wherein the selected one or more memory cells are recognized to operate as one synaptic element.