Multi-Core Synchronization Circuit Reducing Bus Load
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Solution Overview
Problem
In current Bulk Synchronous Parallel (BSP) computing models, the large number of nodes in a multi-core chip leads to increased load on the bus or on-chip network, resulting in significant delay and reduced efficiency of signal transmission between the controller and nodes, necessitating complex software solutions that further reduce overall system efficiency.
Innovation Solution
A synchronization signal generating circuit that processes multiple ready signals simultaneously and transmits signals independently to node groups, reducing the burden on the bus or on-chip network by directly connecting each node to dedicated communication lines, thereby improving synchronization signal transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each node sends messages to the controller through a bus or on-chip network, then the controller can process synchronization signals from all nodes, but the transmission delay increases significantly and the bus load increases when the number of nodes is large
Solution Approach 1:
The patent segments the node set into multiple groups, with each group having a dedicated group ready signal generating sub-circuit. This segmentation reduces the number of nodes that need to communicate through the shared bus, as each group can generate its own ready signal locally. The controller only needs to receive signals from group-level circuits rather than individual nodes, significantly reducing bus load and transmission delay while maintaining synchronization control capability.
2Productivity
If the number of nodes increases to improve parallel processing capability, then data processing speed increases, but the load on the bus or on-chip network increases significantly
Solution Approach 1:
By dividing nodes into groups with dedicated group ready signal generating sub-circuits, the patent reduces the communication burden on the shared bus. Each group generates its own ready signal locally, so the bus only needs to carry aggregated group-level signals rather than individual node signals. This allows the system to scale to more nodes while keeping bus load manageable.
Solution Approach 2:
The patent merges multiple individual node ready signals into a single group ready signal for each node group. The group ready signal generating sub-circuit combines the readiness status of all nodes within its group into one consolidated signal, which is then sent to the controller. This merging approach maintains parallel processing capability across many nodes while significantly reducing the number of signals that must traverse the shared bus.
3Measurement precision
If software complexity is increased to reduce transmission error, then synchronization accuracy improves, but overall system efficiency decreases
Solution Approach 1:
The patent introduces group ready signal generating sub-circuits as intermediary components between individual nodes and the controller. These intermediary circuits perform local signal processing and aggregation, generating consolidated ready signals that reduce transmission errors by minimizing the number of individual signal paths. This hardware-based intermediary approach improves synchronization accuracy without requiring increased software complexity, thereby maintaining system efficiency.
Data Source
AI summary
The present disclosure provides a synchronization signal generating circuit, a chip, and a synchronization method and a synchronization device, based on a multi-core architecture, configured to generate a synchronization signal for M node groups, wherein each of the node groups includes at least one node, and M is an integer greater than or equal to 1. The synchronization signal generating circuit includes: a synchronization signal generating sub-circuit and M group ready signal generating sub-circuits. The M group ready signal generating sub-circuits are in one-to-one correspondence with the M node groups. The synchronization signal generating sub-circuit generates a first synchronization signal based on the first to-be-started signal, wherein the first synchronization signal is configured to instruct the K nodes in the first node group to start synchronization.