Synchronization Circuit with Initial Delay Monitoring for Fast Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor synchronization circuits face challenges in shortening the time required for delay locking and duty cycle compensation operations, which are crucial for high-speed semiconductor integrated circuits.
Innovation Solution
A synchronization circuit design that includes a first delay unit, a second delay unit, and an initial delay monitoring circuit to generate initial delay information, allowing for quick adjustment of delay times and duty cycle compensation using loop circuits and fine mixers, thereby optimizing delay locking and duty cycle correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional delay locking and duty cycle compensation operations are used, then the circuit can achieve proper signal synchronization, but the time required for these operations is too long for high-speed applications
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delay time information in a lookup table before the actual delay locking operation. The initial delay monitoring circuit generates coarse and fine initial delay information in advance, which are then used to quickly set the delay elements without requiring lengthy iterative adjustments during operation.
Solution Approach 2:
The patent replaces the traditional iterative mechanical adjustment mechanism with an information-based system. Instead of physically adjusting delay elements through feedback loops, the system uses pre-computed delay information stored in memory to directly configure the delay elements, substituting mechanical iteration with informational lookup and application.
2Loss of time
If conventional delay locking and duty cycle compensation operations are used, then the circuit can achieve proper signal synchronization, but the time required for duty cycle compensation is too long for high-speed applications
Solution Approach 1:
The patent applies preliminary action by pre-calculating duty cycle compensation values and storing them in the lookup table alongside delay time information. The initial delay monitoring circuit generates both coarse and fine compensation information in advance, enabling immediate application without iterative adjustment during operation.
Solution Approach 2:
The patent replaces the traditional iterative mechanical adjustment mechanism for duty cycle compensation with an information-based system. Pre-computed compensation values are stored and directly applied to control elements, substituting mechanical iteration with informational lookup and application.
3Measurement precision
If more delay elements and feedback mechanisms are added to improve precision, then the synchronization accuracy improves, but the circuit complexity increases
Solution Approach 1:
The patent uses copying by creating a simplified model or representation of the delay characteristics in the form of pre-computed lookup tables. Instead of implementing complex physical delay adjustment mechanisms, the system copies the essential delay information into stored data structures that can be quickly accessed and applied.
Solution Approach 2:
The patent extracts the essential delay and compensation information from complex iterative processes and isolates it into separate pre-computed data structures. By taking out the critical timing information and storing it independently, the system avoids the complexity of real-time computational mechanisms while maintaining precision.
Data Source
AI summary
A synchronization circuit includes a first delay unit configured to delay an input signal by a delay time corresponding to first initial delay information and generate a pre-delayed signal; a second delay unit configured to delay the pre-delayed signal by a delay time corresponding to second initial delay information and generate a delayed signal; and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to internal delayed signals of the first delay unit and the input signal.