Synchronization Circuitry Shift Register Test Data
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Solution Overview
Problem
Conventional synchronization circuitry for mobile FM multiplex broadcasting systems faces challenges in performing tests efficiently, particularly when reception conditions are poor, due to the lengthy time required to detect block and frame synchronization.
Innovation Solution
The synchronization circuitry incorporates a switcher and controller to selectively input either received data or the last stage's output to the shift register, allowing for the use of test data to shorten the testing time and reduce the data size from 288 bits per block to 32 bits, enabling faster block and frame synchronization testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional synchronization circuitry uses full frame data (288 bits per block) for testing, then testing accuracy is maintained, but testing time becomes excessively long
Solution Approach 1:
The patent extracts only the essential block identity code (16 bits) from the full frame data (288 bits) for testing purposes. By taking out only the necessary synchronization information and ignoring the remaining data, the system achieves fast testing without compromising synchronization detection accuracy, directly resolving the contradiction between testing time and accuracy.
Solution Approach 2:
The patent creates a simplified copy of the frame data structure that contains only the block identity codes necessary for synchronization testing. This copy allows the system to perform rapid testing operations while maintaining the essential synchronization detection capability, effectively reducing testing time without losing measurement precision.
2Productivity
If the shift register stores complete frame data for synchronization testing, then synchronization can be detected accurately, but the data processing complexity and time increase
Solution Approach 1:
The patent extracts only the block identity code portion (16 bits) from the complete frame data structure for storage and processing in the shift register. This extraction reduces the data processing complexity significantly while maintaining the ability to detect synchronization, thereby improving productivity without increasing device complexity.
Solution Approach 2:
The patent segments the frame data into essential synchronization information (block identity codes) and non-essential data. By processing only the segmented essential portion, the system achieves faster synchronization testing with reduced data processing complexity, directly addressing the contradiction between productivity and device complexity.
3Loss of time
If conventional testing methods process all 288 bits per block, then comprehensive testing is achieved, but the testing duration becomes prohibitively long
Solution Approach 1:
The patent extracts only the block identity code (16 bits) which contains the essential synchronization information needed for comprehensive testing. By taking out only this critical portion, the system achieves fast testing with maintained comprehensive coverage for synchronization detection, resolving the contradiction between testing duration and coverage.
Solution Approach 2:
The patent changes the testing parameter from processing full frame data (288 bits) to processing only block identity codes (16 bits). This parameter change reduces the testing duration dramatically while maintaining adequate testing comprehensive coverage for synchronization detection, effectively resolving the time versus coverage contradiction.
Data Source
AI summary
Synchronization circuitry includes a switcher controlled by a central processing unit to select either received data or an output of the last stage of a shift register to input the selected data to the input of the first stage of the shift register. The central processing unit is able to write test data to the shift register in a short time, so that the shift register can test block synchronization and frame synchronization by shifting CPU data in response to a clock signal. The synchronization circuitry is therefore capable of performing a synchronous operation with a 16-bit shift clock signal, so that it can shorten the time required for design and tests.