Synchronous Clear Emulation Circuit Without Gated Clock Skew
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Solution Overview
Problem
Integrated circuits, such as FPGAs, face inaccuracies in static timing analysis due to clock skew caused by gated clock signals, which are not present in all registers, limiting their functionality.
Innovation Solution
A synchronous clear emulation circuit is implemented using an asynchronous clear port, with a clock follower circuit that does not gate the clock signal, reducing the likelihood and impact of clock skew, thereby emulating a synchronous clear port without the need for a dedicated synchronous clear port.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a gated clock signal is used in registers, then the synchronous clear function can be implemented, but clock skew is introduced causing inaccurate static timing analysis
Solution Approach 1:
A dedicated synchronous clear circuit is introduced as an intermediary component that receives the clock signal directly from the clock source, bypassing the register's gated clock path. This separate circuit generates the clear signal independently, eliminating the clock skew problem while maintaining the synchronous clear function.
Solution Approach 2:
The synchronous clear function is segmented from the main register structure into a separate dedicated circuit. This segmentation allows the clear function to operate with its own clock timing independent of the register's gated clock signal, thereby avoiding clock skew issues in timing analysis.
2Adaptability or versatility
If a synchronous clear port is added to the register, then the clear function is provided, but device complexity and cost increase
Solution Approach 1:
The dedicated synchronous clear circuit is designed to serve multiple registers simultaneously. By sharing this clear circuit across multiple register instances, the additional complexity is amortized, providing the synchronous clear function without proportionally increasing overall device complexity or cost.
3Ease of operation
If a two-input gate is used to gate the clock signal, then clock control is achieved, but clock skew is created
Solution Approach 1:
A dedicated synchronous clear circuit acts as an intermediary that receives and processes the clock signal separately from the register's gated clock path. This intermediary approach maintains clock control functionality while eliminating the timing disruptions caused by two-input gating operations.
Data Source
AI summary
A synchronous clear emulation circuit is provided. The synchronous clear emulation circuit includes a register having an asynchronous clear port. Moreover, the synchronous clear emulation circuit is configured to emulate a synchronous clear port by using the asynchronous clear port. The synchronous clear port is emulated by outputting a data output signal that is synchronous with the clock signal and the data output signal is based on an asynchronous clear signal received at the asynchronous clear port. The asynchronous clear port performs a function of the asynchronous clear port without the synchronous clear port implemented within the register.