Synchronized Clocks for Inter-Clock Domain Transition Defect Detection
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Solution Overview
Problem
Conventional clock control circuits are limited in generating synchronized pulses across multiple clock domains, making inter-clock domain transition testing difficult, especially at higher frequencies where pulses need to be generated on-chip due to tester electronics limitations.
Innovation Solution
The implementation of a system that generates synchronized launch and capture pulses across multiple clock domains using a dedicated launch trigger, allowing for synchronized clock signals to detect inter-clock domain transition defects, which includes a first circuit to generate a launch signal synchronized with a first clock signal and a second circuit to generate pulses based on a second clock signal, ensuring integer multiple frequencies and initial pulse synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pulses are generated on-chip for clock frequencies greater than 200 MHz, then the limitation of tester electronics is overcome, but generating synchronized pulses across multiple clock domains becomes difficult
Solution Approach 1:
The system divides the clock domain into multiple segments (first clock domain and second clock domain) with separate clock control circuits. Each circuit generates pulses independently for its respective clock domain, then these segmented pulse streams are combined through synchronization logic to achieve coordinated operation across domains without requiring a single complex control circuit
Solution Approach 2:
A launch signal acts as an intermediary between the first and second clock control circuits. The first circuit generates this launch signal synchronized to its clock domain, and the second circuit uses it to synchronize its pulse generation. This intermediary signal bridges the two independent clock domains, enabling synchronized operation without direct coupling between the clock sources
2Device complexity
If conventional clock control circuits are used, then circuit simplicity is maintained, but inter-clock domain transition testing capability is lost
Solution Approach 1:
The clock control circuits are designed with multi-functionality: they can operate independently for single-clock domain testing and also coordinate through the launch signal mechanism for inter-clock domain transition testing. This universal design allows the same circuit structure to serve multiple testing purposes without requiring separate dedicated circuits for different test types
Solution Approach 2:
The system performs preliminary synchronization by generating the launch signal in advance within the first clock domain before capturing transitions in the second clock domain. This preliminary action establishes the timing reference needed for coordinated operation, allowing the capture pulse to be properly synchronized to detect transitions at the correct moment without requiring complex real-time coordination
Data Source
AI summary
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a launch signal synchronized with a first clock signal in a first clock domain. The second circuit may be configured to (i) receive a second clock signal in a second clock domain and (ii) generate a plurality of pulses in each of a third clock signal and a fourth clock signal based on the second clock signal and the launch signal. A frequency of the pulses in the fourth clock signal may be an integer multiple of another frequency of the pulses in the third clock signal. An initial one of each of the pulses in the third clock signal and the fourth clock signal may be synchronized with each other.