Synchronous Clocking Serial Memory Interface
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Solution Overview
Problem
Serial memory interfaces face issues with DC balance, consecutive identical digits (CIDs), and clock data recovery due to the limitations of AC-coupled capacitors on chips, leading to charge buildup, latency, and increased bit error rates, especially with traditional asynchronous clocking and large CIDs.
Innovation Solution
Implementing synchronous clocking across components with a designated master serial link for encoded data streams and slave links for un-encoded, scrambled data streams, allowing for on-chip AC-coupled interfaces and reducing latency by distributing a synchronous system clock, thereby ensuring DC balance and deterministic CIDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If AC-coupled capacitors are provided on chips to enable interoperability, then device compatibility is improved, but the number of consecutive identical digits is limited due to capacitor size constraints
Solution Approach 1:
The patent segments the serial link into multiple independent lanes (e.g., 4 lanes), each capable of transmitting data independently. This segmentation allows the system to overcome the CID limitation of individual lanes by distributing data across multiple lanes, effectively increasing the overall data transmission capability while maintaining compatibility with AC-coupled capacitor constraints.
Solution Approach 2:
The patent transitions from a single serial link to a multi-lane parallel structure, adding a spatial dimension to data transmission. By organizing multiple serial lanes in parallel and using lane interleaving techniques, the system effectively increases the data stream capacity without requiring larger capacitors, thus resolving the contradiction between capacitor size constraints and CID limitations.
2Adaptability or versatility
If traditional asynchronous clocking is used between transmitter and receiver, then frequency tolerance is improved, but latency increases due to phase build up compensation
Solution Approach 1:
The patent implements preliminary clock synchronization between transmitter and receiver before data transmission begins. By pre-aligning the clock phases and frequencies of both ends, the system eliminates the need for runtime phase build-up compensation, thereby reducing latency while maintaining frequency tolerance through the established synchronous relationship.
Solution Approach 2:
The patent replaces the traditional asynchronous clocking mechanism with a synchronous clocking system that uses a shared clock reference. This substitution eliminates the mechanical phase drift issue inherent in asynchronous systems, reducing the need for compensation circuitry and associated latency while maintaining robust frequency tolerance through the synchronized clock distribution.
3Adaptability or versatility
If AC-coupled capacitors are used in serial interfaces, then interoperability between different vendors and process technologies is improved, but DC baseline wander occurs due to charge buildup
Solution Approach 1:
The patent implements periodic DC balancing sequences in the data stream, inserting specific bit patterns at regular intervals that ensure equal numbers of high and low transitions. This periodic action prevents charge buildup on the AC-coupled capacitors, maintaining DC baseline stability while preserving interoperability benefits across different vendors and process technologies.
Solution Approach 2:
The patent incorporates DC balance monitoring and control mechanisms that track the charge state of AC-coupled capacitors and dynamically adjust the data transmission parameters accordingly. This feedback system ensures that DC baseline wander is compensated in real-time, maintaining signal integrity and interoperability across diverse hardware platforms while preventing charge buildup issues.
Data Source
AI summary
A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.