Synchronously-Switched Comparator for Four-Wire Vector Demodulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed digital interconnection systems face limitations in achieving reliable, error-free data transfer at rates beyond 20 Gbps due to data skew, inter-symbol interference, and increased complexity and power consumption, which conventional signaling methods struggle to address effectively.
Innovation Solution
The implementation of a system using vector signaling codes, specifically Ensemble NRZ (ENRZ) and duobinary encoding, combined with Hadamard transforms and synchronously-switched multi-input demodulating comparators, to create multiple frequency-based channels over a four-wire bus, enabling robust data transfer at 56 Gigabits per second per wire with reduced ISI and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional signaling methods are used for high-speed digital interconnection, then data transfer rate can be increased, but data skew and inter-symbol interference increase causing errors
Solution Approach 1:
The patent segments the data transfer problem by using multiple parallel wires (four-wire bus) to transmit different components of vector signaling codes simultaneously. This segmentation allows higher aggregate data rates while each individual wire operates at manageable speeds, reducing per-wire skew and ISI issues.
Solution Approach 2:
The patent changes the signaling parameters by implementing vector signaling codes (ENRZ and duobinary encoding) instead of conventional signaling. This parameter change transforms how data is encoded and transmitted, enabling higher speeds while maintaining reliability through the mathematical properties of the coding schemes.
2Productivity
If data transfer rate is increased beyond 20 Gbps, then productivity improves, but complexity and power consumption increase
Solution Approach 1:
The synchronously-switched multi-input demodulating comparator performs multiple functions: it demodulates carrier-modulated symbols, decodes vector signaling codes, and handles multiple input wires simultaneously. This multi-functionality reduces the need for separate dedicated circuits for each task, thereby reducing overall system complexity.
Solution Approach 2:
The patent merges the demodulation and comparison functions into a single synchronously-switched multi-input demodulating comparator circuit. This consolidation integrates multiple operations that would traditionally require separate components, reducing device complexity while maintaining high-speed performance.
3Ease of manufacture
If conventional signaling methods are used, then ease of implementation is maintained, but inter-symbol interference increases at high speeds
Solution Approach 1:
The patent changes the signaling parameters by implementing vector signaling codes (ENRZ and duobinary encoding) instead of conventional signaling. This parameter change transforms how data is encoded and transmitted, enabling higher speeds while maintaining reliability through the mathematical properties of the coding schemes.
Solution Approach 2:
The patent converts the harmful effect of inter-symbol interference by using duobinary encoding, which intentionally shapes the signal spectrum to reduce high-frequency content that causes ISI. The encoding scheme transforms potential interference into a controlled signal characteristic that can be managed at the receiver.
Data Source
AI summary
Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.