Synchronous Differential Signaling Protocol for Low Latency
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Solution Overview
Problem
Conventional communications over wires and channels in integrated circuits or on circuit boards introduce significant latency, degrading high-bandwidth applications such as HD audio and real-time data processing, particularly in consumer devices like mobile phones and personal computers, where low latency data transfer is crucial.
Innovation Solution
A synchronous, differential signaling protocol that enables high-bandwidth and low-latency communications over a wired connection between a master and slave device, featuring flexible data mapping, low power modes, burst configuration, and robust auto-link-lock mechanisms, allowing for efficient data transfer with reduced clock circuitry and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional wired communications are used, then device complexity is reduced, but latency increases significantly
Solution Approach 1:
The communications protocol segments data into fixed-size frames with specific bit allocations for different functions (audio data, control information, synchronization). This segmentation enables precise timing and reduces latency by processing data in discrete, time-synchronized units rather than continuous streams.
Solution Approach 2:
The protocol performs preliminary actions by pre-establishing synchronization bits and clock reference signals at the beginning of each frame. This preliminary synchronization eliminates the need for complex real-time clock recovery during data transmission, reducing overall latency while maintaining manageable device complexity.
2Productivity
If synchronous differential signaling is implemented, then communication efficiency increases, but device complexity increases
Solution Approach 1:
The differential signaling protocol implements multi-functionality by encoding multiple types of information (audio data, control commands, synchronization signals, error detection) within a single frame structure. This universal approach increases communication efficiency by reducing protocol overhead while the standardized frame format keeps device complexity manageable through reuse of the same structural elements.
Solution Approach 2:
The protocol achieves high efficiency by changing key parameters: using differential voltage levels for signaling, implementing synchronous sampling at fixed rates, and allocating bits deterministically within frames. These parameter changes optimize communication throughput while the regular, predictable structure maintains acceptable device complexity.
3Reliability
If clock reference bits are transmitted in both directions, then synchronization is improved, but communication overhead increases
Solution Approach 1:
The protocol applies asymmetry by transmitting clock reference bits primarily in one direction (from master to slave) rather than symmetrically in both directions. The slave device generates its own clock based on the received reference, while the master device uses its internal clock. This asymmetric approach maintains synchronization reliability while reducing communication overhead by eliminating redundant clock bit transmission.
4Adaptability or versatility
If flexible data mapping to bit slots is provided, then adaptability increases, but protocol complexity increases
Solution Approach 1:
The protocol implements dynamics by allowing flexible allocation of bit slots within the fixed frame structure. Different frame types can assign different numbers of bits to audio data, control information, and other functions based on current communication needs. This dynamic adaptability is achieved through predefined allocation rules rather than complex runtime negotiation, maintaining manageable protocol complexity while providing versatile data mapping capabilities.
Data Source
AI summary
Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.