SYNC Generation Circuit for USB Hub Signal Integrity

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Solution Overview

Problem

In serial communication systems, such as USB, the introduction of a USB hub or similar devices in the signal path can reduce the number of SYNC bits, making it difficult to pass authentication tests due to signal degradation and parasitic capacitance, leading to failed standard authentication tests.

Innovation Solution

A circuit device with a processing circuit that includes a SYNC generation circuit, which generates an m-bit SYNC and outputs it to the second bus, ensuring that packets have the required number of SYNC bits for compliance with the serial communication standard, even if the input has fewer bits, thereby enabling successful authentication tests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a USB hub or similar device is provided in the signal path to connect multiple devices or suppress signal degradation, then the adaptability and signal quality are improved, but the number of SYNC bits is reduced, causing authentication test failures

Engineering Contradiction:
Improveability to connect multiple devicesVSAvoidnumber of SYNC bits
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent introduces a SYNC bit supplementation mechanism as an intermediary between the USB hub and the authentication test. The hub initially reduces SYNC bits to minimize signal degradation, but a supplementation circuit adds the required number of SYNC bits before the authentication test, allowing both signal quality improvement and authentication compliance

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent dynamically changes the number of SYNC bits based on the operational context. During normal data transmission, fewer SYNC bits are used to reduce signal degradation. During authentication tests, additional SYNC bits are supplied to meet the required threshold, thus adapting the parameter to different operational requirements

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If a USB hub is inserted in the signal path to enable multiple device connections, then the versatility is improved, but the authentication test compliance deteriorates due to reduced SYNC bits

Engineering Contradiction:
Improvedevice connection capabilityVSAvoidauthentication test compliance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent detects authentication test packets in advance and prepares supplementary SYNC bits before the authentication test occurs. When an authentication test packet is detected, the system proactively adds the required number of SYNC bits to ensure compliance, rather than attempting to fix the problem after authentication failure

Inventive Principle:
Principle #10Preliminary action

3Object-affected harmful factors

If signal path devices are added to suppress degradation, then the signal quality is improved, but the SYNC bit count is reduced, leading to authentication failures

Engineering Contradiction:
Improvesignal degradationVSAvoidSYNC bit number
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent extracts the SYNC bit supplementation function from the main data transmission path. A separate supplementation circuit independently adds the required SYNC bits without interfering with the primary signal transmission, thus maintaining signal quality improvements while separately addressing the SYNC bit count requirement

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11416438B2Circuit device, electronic device, cable harness, and data transfer method
Publication Date: 2022.08.16 SEIKO EPSON CORP
  • US11416438B2 patent drawing
  • US11416438B2 patent drawing
  • US11416438B2 patent drawing

AI summary

A circuit device includes a first physical layer circuit to which a first bus is connected, a second physical layer circuit to which a second bus is connected, and a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transmitted to the second bus via the second physical layer circuit. The processing circuit includes a SYNC generation circuit that generates an m-bit SYNC, and when the packet is received from the first bus, the processing circuit outputs the m-bit SYNC to the second physical layer circuit.