Sync Signal Glitch Filtering in Graphic Controllers

The patent applies preliminary action by implementing a holding circuit that anticipates and prevents glitch-induced errors before they affect resolution detection. The holding circuit maintains the detected state for a predetermined period after a valid transition, proactively blocking false pulses before they can be misinterpreted as legitimate signal edges. This preemptive measure ensures accurate resolution detection without sacrificing the rapid response capability of the detection circuit.

The patent employs an intermediary approach by inserting a holding circuit between the detection circuit and the resolution determination logic. This intermediary component acts as a buffer that filters out glitch-induced false transitions while allowing legitimate signal edges to pass through. The holding circuit uses a simple latch mechanism with a predetermined time constant, providing effective glitch rejection without introducing significant circuit complexity or processing overhead.

The patent applies periodic action through the holding circuit's time-limited blocking mechanism. The circuit operates in periodic cycles: when a valid transition is detected, the holding circuit activates and blocks subsequent transitions for a predetermined period, then automatically resets to accept new transitions. This periodic blocking pattern effectively filters glitches while maintaining rapid response to legitimate signal changes, as the block duration is carefully calibrated to match typical glitch widths without extending to valid transition intervals.