Sync Group-Aware Design Rule Checking for Integrated Circuit Density
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Solution Overview
Problem
Current design rule check processes for integrated circuits do not adequately account for synchronous voltage behavior, leading to unnecessary spacing violations and limitations in the density of processing elements within semiconductor devices.
Innovation Solution
The method involves identifying sync groups with synchronous voltage levels, generating a physical design with sync group constraints, and performing design rule checking using transferred sync group information to apply more stringent or relaxed spacing requirements based on the synchronous behavior of circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional design rule checking is used without sync group constraints, then manufacturing simplicity is maintained, but spacing violations occur unnecessarily and processing element density is limited
Solution Approach 1:
The design rule checking process is segmented into conventional DRC and sync group-aware DRC components. Sync groups are identified and classified separately, allowing differential spacing rules to be applied to different net categories (synchronous vs. asynchronous), thereby increasing processing element density while maintaining manufacturing precision through targeted spacing control.
Solution Approach 2:
Different spacing rules are applied locally based on the electrical characteristics of specific net groups. Synchronous nets receive relaxed spacing requirements while asynchronous nets maintain conventional spacing, allowing closer placement of processing elements connected by synchronous nets without compromising manufacturing precision for critical asynchronous connections.
2Measurement precision
If synchronous voltage behavior is not accounted for in verification processes, then verification process simplicity is maintained, but design rule analysis accuracy is reduced
Solution Approach 1:
Sync group information is extracted and associated with physical design elements during the layout phase, before final design rule checking. This preliminary action prepares the data structures and constraints needed for accurate sync group-aware DRC, improving measurement precision while managing verification process complexity through staged processing.
Solution Approach 2:
A sync group constraint system acts as an intermediary layer between the physical design and design rule checking processes. This intermediary captures synchronous voltage behavior characteristics and translates them into applicable spacing constraints, enhancing design rule analysis accuracy without directly complicating the core verification process.
Data Source
AI summary
An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.