Synchronous I/O Clock Gating for Low-Cost Debug Interface Security

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Solution Overview

Problem

Inexpensive electronic devices lack the capability to disable or enable synchronous input/output interfaces, making them vulnerable to unauthorized access and compromising security, unlike expensive high-end devices which often have such provisions.

Innovation Solution

An electronic device with a filter circuit that can be activated or deactivated using an activation signal or deactivation signal to control the operation of a synchronous I/O interface, allowing for the blocking or passing of a clock signal to the interface, thereby enabling or disabling its operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If an exposed synchronous I/O interface is provided in an inexpensive electronic device, then the device can perform debug and configuration operations, but the device becomes vulnerable to unauthorized access and security breaches

Engineering Contradiction:
Improvedebug capabilityVSAvoidsecurity vulnerability
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

A filter circuit is introduced as an intermediary component between the external environment and the synchronous I/O interface. This filter circuit selectively blocks or passes clock signals based on control signals, thereby mediating access to the debug interface and preventing unauthorized access while maintaining legitimate debug functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The synchronous I/O interface is transformed from a static, always-accessible interface to a dynamic interface whose accessibility changes based on control signals. The filter circuit enables the interface to switch between enabled and disabled states, allowing the system to adapt its security posture according to operational requirements

Inventive Principle:
Principle #15Dynamics

2Object-affected harmful factors

If a filter circuit is added to control the synchronous I/O interface, then security is enhanced by blocking unauthorized access, but the device complexity increases

Engineering Contradiction:
Improvesecurity protectionVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The filter circuit is implemented using simple, inexpensive components such as capacitors, resistors, and transistors that can be easily integrated into the existing device. These basic electronic components provide the necessary security function without requiring complex or expensive security modules

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The filter circuit serves multiple functions: it acts as a security mechanism to block unauthorized access, while also providing control functionality through the activation and deactivation signals. This multi-functionality reduces the need for separate dedicated security components, thereby limiting the increase in device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution provides enhanced security for inexpensive devices by allowing easy control of built-in debug circuitry without modifying the chip, effectively preventing illegitimate access to confidential information at a low cost.

Implementation Method 1

a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the clock signal, or (b) the deactivation signal to deactivate the filter circuit to pass the clock signal

Methodology Applied
Scientific EffectFilter circuit: Filter (electronic)

Data Source

PatentEP3995983A1Controlling synchronous I/O interface
Publication Date: 2022.05.11 U-BLOX
  • EP3995983A1 patent drawingFigure 1~2
  • EP3995983A1 patent drawingFigure 3~4
  • EP3995983A1 patent drawingFigure 5

AI summary

An electronic device includes: a first input node configured to receive a clock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the clock signal, or (b) the deactivation signal to deactivate the filter circuit to pass the clock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.