Synchronous Memory Address Receiver Power Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Synchronous memory address receivers must remain permanently 'on' due to simultaneous receipt of address and command signals, leading to significant power consumption.
Innovation Solution
Implementing a system where address receivers are initially in an off state, with a delayed address signal relative to the command signal, allowing for dynamic enabling based on command logic, using a decoder to generate a receiver enable signal and power on only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address receivers are kept permanently on to receive address signals simultaneously with command signals, then the memory system can operate correctly with proper signal reception, but power consumption increases significantly
Solution Approach 1:
The patent applies dynamics by transitioning the address receiver from a static permanently-on state to a dynamic state that can be selectively enabled or disabled. The address receiver is controlled by an enable signal that activates it only during specific clock cycles when address signals need to be received, allowing the system to adapt its operational state based on real-time requirements.
Solution Approach 2:
The patent implements periodic action by enabling the address receiver only during specific periodic intervals (certain clock cycles) rather than continuously. The enable signal activates the address receiver in a periodic manner synchronized with the clock signal, allowing it to operate only when necessary for receiving address signals while remaining inactive during other cycles to reduce power consumption.
2Productivity
If address signals and command signals are received in the same clock cycle, then the memory operation timing is simplified, but address receivers cannot be powered down and consume excessive power
Solution Approach 1:
The patent applies segmentation by separating the reception timing of command signals and address signals into different clock cycles. Command signals are received in one clock cycle while address signals are received in a subsequent clock cycle, dividing what was previously a simultaneous reception into distinct temporal segments. This allows the address receiver to be disabled during command reception cycles and activated only when address signals are expected.
Solution Approach 2:
The patent implements preliminary action by decoding the command signal in advance to determine whether an address signal will follow, and enabling the address receiver beforehand in the next clock cycle. The decoder analyzes the command signal and generates an enable signal that activates the address receiver in preparation for the upcoming address signal, ensuring the receiver is ready before the address signal arrives.
3Use of energy by moving object
If decoding logic is added to selectively latch or release addresses, then power consumption is reduced by enabling address receivers only when needed, but device complexity increases
Solution Approach 1:
The patent applies merging by combining the decoder and address receiver enable control into a unified scheme. The same decoding logic that determines command execution also controls the address receiver enable signal, merging two control functions into one integrated approach. This reduces overall system complexity compared to having separate control mechanisms for command decoding and receiver enabling.
Solution Approach 2:
The patent implements universality by making the decoder serve multiple functions: it decodes command signals to determine operation type and simultaneously generates the enable signal for the address receiver. This multi-functional approach eliminates the need for separate control logic, reducing device complexity while achieving power savings through selective receiver enabling.
Data Source
AI summary
A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.