Synchronization Module for Asynchronous Motor Control
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Solution Overview
Problem
Asynchronous timing between FPGA commands and motor control systems in electric motor control systems requires computationally intensive or energy taxing solutions, necessitating improved event synchronization methods.
Innovation Solution
A system comprising a first control system operating at a low clock speed and a second control system operating at a higher clock speed, synchronized by a synchronization module that samples the clock speed, tracks motor speed data, calculates errors, and generates new duty cycle commands, allowing for synchronized output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional asynchronous control methods are used between FPGA and motor control systems, then system functionality is maintained, but computational complexity and energy consumption increase significantly
Solution Approach 1:
The patent introduces a synchronization module as an intermediary component between the FPGA and motor control system. This module receives commands from the FPGA, synchronizes them with the motor control system's clock domain, and ensures proper timing alignment. By using this intermediary, the system achieves efficient asynchronous communication without requiring computationally intensive solutions, thereby reducing energy consumption while maintaining full system functionality.
2Measurement precision
If computationally intensive solutions are used to handle asynchronous timing, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex computational synchronization methods with a simpler clock-domain-crossing synchronization mechanism. Instead of using computationally intensive algorithms to handle asynchronous timing, the invention employs a dedicated synchronization module that uses register-based timing alignment and clock domain crossing techniques. This substitution reduces computational complexity while maintaining synchronization accuracy through hardware-level timing control.
3Adaptability or versatility
If traditional asynchronous control architectures are used, then system flexibility is maintained, but resource utilization efficiency decreases
Solution Approach 1:
The patent segments the control system into distinct synchronized domains: an FPGA command generation domain, a synchronization module domain, and a motor control system domain. Each segment operates at its optimal clock speed while the synchronization module ensures proper coordination between them. This segmentation allows each component to be optimized independently, maintaining system flexibility while improving overall resource utilization efficiency by eliminating the need for overly complex asynchronous handling throughout the entire system.
Data Source
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AI summary
A system (100) includes a first control system (103) configured to operate at a first clock speed, a second control system (105) configured to provide an output to the first control system (103) and configured to operate at a second clock speed different from the first clock speed, and a synchronization module (107) operatively connecting the first control module to the second control module and configured to synchronize the first control system and the second control system such that the output of the second control system is timed to synchronize with the first clock speed.