Synchronization Module for Multi-Tile Processing Arrays
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Solution Overview
Problem
In parallel computing using multiple processor tiles, existing bulk synchronous parallel (BSP) protocols face challenges in synchronizing workloads effectively, leading to inefficiencies in data exchange and computation phases, particularly in machine intelligence applications where dependencies between nodes require deterministic timing guarantees.
Innovation Solution
A computer architecture with a synchronisation module and switching fabric that allows processing units to execute local programs according to a common clock, enabling time deterministic data packet transmission and reception between tiles without destination identifiers, ensuring synchronized transitions between compute and exchange phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BSP protocols are used for synchronization, then computation can proceed on multiple tiles, but deterministic timing guarantees cannot be ensured due to synchronization overhead and variability
Solution Approach 1:
The patent applies preliminary action by pre-configuring switching fabric connections and data routing paths before the compute phase begins. The switching fabric is set up in advance to establish deterministic data transmission paths, eliminating the need for runtime synchronization negotiations and ensuring predictable timing without overhead.
Solution Approach 2:
The patent extracts the synchronization function from the traditional BSP protocol sequence and replaces it with a dedicated synchronisation module that operates independently. This module uses a common clock signal distributed to all tiles to enforce phase transitions, separating the timing control from the computation and exchange operations themselves.
2Speed
If data packets include destination identifiers for routing, then data can be directed to specific recipient tiles, but transmission time becomes uncertain due to routing decisions and switching complexity
Solution Approach 1:
The patent applies preliminary action by pre-establishing routing paths through the switching fabric before data transmission begins. The synchronisation module pre-configures the switching fabric to connect specific source tiles to specific recipient tiles for the upcoming exchange phase, eliminating runtime routing decisions and ensuring deterministic transmission timing.
3Reliability
If barrier synchronization is enforced between compute and exchange phases, then all tiles can be synchronized, but tiles that complete early must wait, reducing productivity
Solution Approach 1:
The patent applies periodic action by using a common clock signal that periodically triggers phase transitions across all tiles. The synchronisation module uses this clock to enforce compute phase and exchange phase boundaries, allowing tiles to progress in lockstep while maintaining the ability to utilize idle periods through pipeline techniques and overlapping operations.
4Measurement precision
If a common clock is used to govern all processing units, then deterministic timing can be achieved, but the system becomes more complex with additional synchronization infrastructure
Solution Approach 1:
The patent applies universality by designing the synchronisation module to perform multiple functions: distributing the common clock signal, tracking compute phase completion status across all tiles, controlling exchange phase transitions, and managing switching fabric configuration. This multi-functional approach consolidates synchronization complexity into a single dedicated module rather than distributing it across all processing units.
Data Source
AI summary
The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection wires, the data packet being destined for at least one recipient processing unit but having no destination identifier, and at a predetermined switch time the recipient processing unit executes a switch control instruction from its local program to control its switching circuitry to connect its input set of wires to the switching fabric to receive the data packet at a receive time, the transmit time and, switch time and receive time being governed by the common clock with respect to the synchronisation signal.