Synchronous Rectifier Controller Adaptive Threshold Timing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing synchronous rectifier control schemes struggle to accurately control MOSFETs with low ohmic resistance, leading to inefficiencies in switched mode power supplies, especially at low power output levels due to insufficient potential drop for precise measurement.

Innovation Solution

A closed-loop adaptive timing control scheme for synchronous rectifier controllers that adjusts the first threshold level, compensating for delays and offsets caused by component tolerance and temperature variations, allowing accurate operation with very low ohmic MOSFETs without requiring an accurate reference threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If MOSFETs with lower ohmic resistance are used to reduce conduction losses, then efficiency is improved, but the potential drop across the MOSFET becomes insufficient for accurate measurement by existing control schemes

Engineering Contradiction:
Improveconduction lossesVSAvoidpotential drop measurement
Core Design Contradiction:
Loss of energyVSMeasurement precision

Solution Approach 1:

The patent implements dynamic threshold adjustment where the reference threshold voltage is not fixed but adapts based on operating conditions. The controller dynamically modifies the threshold level to maintain accurate timing control across varying MOSFET resistance values, enabling precise measurement even when the potential drop is very small due to low ohmic resistance MOSFETs.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the parameter of reference threshold voltage from a static value to a dynamically adjustable parameter. By modifying the threshold level according to the actual potential drop across the MOSFET, the system maintains measurement precision regardless of how low the MOSFET resistance becomes, thus resolving the contradiction between low conduction losses and measurement accuracy.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If synchronous rectifier timing control is made more precise to improve efficiency, then system performance is improved, but the complexity of the control scheme increases

Engineering Contradiction:
Improvesystem efficiencyVSAvoidcontrol scheme complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent employs feedback mechanisms where the controller continuously monitors the potential drop across the MOSFET and adjusts the reference threshold accordingly. This closed-loop approach enables precise timing control without requiring overly complex open-loop control schemes, as the feedback automatically compensates for variations and maintains optimal operation.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The control scheme is designed to be self-adjusting, where the system automatically adapts the threshold level based on its own operating conditions without requiring external intervention or complex external control circuitry. This self-service capability achieves high precision timing control while minimizing the added complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP2876798B1Synchronous rectifier controller
Publication Date: 2019.09.18 NXP BV
  • EP2876798B1 patent drawingFigure 1
  • EP2876798B1 patent drawingFigure 2a~2b
  • EP2876798B1 patent drawingFigure 3a~3b

AI summary

A synchronous rectifier controller (424) for a switched mode power supply (200a; 200b) comprising a transformer (202) with a secondary side winding (206a) and a synchronous rectifier transistor (222a; 222b) with a gate, a source and a drain, the source and drain providing a conduction channel coupled to the secondary side winding (206a), the controller (424) comprising: an input terminal (460) for receiving an input signal (532) related to a voltage at the drain; an output terminal (462) configured to provide an output signal (542) for setting a logic state (467) of the gate; and circuitry (464) having a first threshold (452, 552) and a second threshold (454, 554), the circuitry (464) configured to: generate the output signal (542) in accordance with a comparison between the input signal (632) and the first threshold (452, 552); determine a time period (549) in accordance with the comparison between the input signal (532) and the first threshold (452, 552) and in accordance with a comparison between the input signal (532) and the second threshold (454, 554); and set the first threshold in accordance with the time period (549).