Synchronization Register Bitwise Coordination for Parallel Processing
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Solution Overview
Problem
Existing parallel processing synchronization methods, such as hardware synchronization barriers, face inefficiencies in coordinating multiple processor cores due to reliance on network communication, leading to asynchronous and delayed resumption of suspended threads.
Innovation Solution
A method involving configuration of a synchronization register where each processing unit has a distinct bit position, allowing threads to suspend and resume based on bitwise OR operations and local messaging, enabling rapid and coordinated thread resumption without network dependency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If network communication is used for synchronization between processing units, then coordination between multiple cores can be achieved, but synchronization delays and asynchronous thread resumption occur
Solution Approach 1:
The patent extracts the synchronization functionality from network-dependent operations and implements it locally within each processing unit using synchronization registers. Each processing unit maintains its own synchronization state independently, eliminating the need for network communication during the actual synchronization operation, thus removing the source of delays while maintaining coordination reliability
Solution Approach 2:
The patent performs preliminary configuration of synchronization registers with expected values before threads reach synchronization points. Processing units pre-load their synchronization registers with the expected pattern of bits that should be set when all threads arrive, allowing for immediate local comparison and thread resumption without waiting for network confirmation
2Adaptability or versatility
If hardware synchronization barriers with mailboxes are used, then synchronization mode can be implemented, but bitwise OR operations and master core notification create complexity
Solution Approach 1:
The patent segments the centralized mailbox approach into distributed synchronization registers, with each processing unit having its own independent register. This segmentation eliminates the single point of complexity (the master-controlled mailbox) and distributes the synchronization logic across multiple independent units, reducing overall system complexity while maintaining adaptability
Solution Approach 2:
Each processing unit independently manages its own synchronization register without requiring master core control or notification. The units autonomously perform the bitwise OR operation on their local registers and self-determine when synchronization is complete, eliminating the complex master-slave control architecture while preserving synchronization functionality
Data Source
AI summary
A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.