Synchronization Signal Detection Chip Using Sequence Segmentation
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Solution Overview
Problem
In wireless communication systems, detecting synchronization signals using all possible combinations of Zadoff Chu sequences, Hadamard matrices, and cyclic shifts is inefficient in terms of processing time and energy consumption.
Innovation Solution
A chip with a processor and memory that performs descrambling by multiplying the received synchronization signal with sequences and their complex conjugates, applies inverse fast Fourier transform to cumulative sums of descrambled sequences, and groups sequences to reduce the number of operations required for detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all possible synchronization signals are used for descrambling, then detection accuracy is improved, but processing time increases
Solution Approach 1:
The patent segments the set of all possible synchronization signals into multiple groups. Instead of performing descrambling with all possible signals at once, the method divides them into manageable groups and processes each group separately. This segmentation reduces the processing time while maintaining detection accuracy by systematically checking each group.
Solution Approach 2:
The patent performs preliminary descrambling operations with a subset of synchronization signals before final detection. By pre-processing with selected groups of sequences and identifying candidate signals early, the system reduces the overall processing time while ensuring accurate detection through subsequent verification steps.
2Measurement precision
If all possible synchronization signals are used for descrambling, then detection accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent segments the exhaustive set of synchronization signals into multiple groups, processing only one group at a time. This approach significantly reduces energy consumption by avoiding simultaneous processing of all possible signals, while maintaining detection accuracy through systematic group-by-group evaluation.
Solution Approach 2:
The patent performs partial descrambling with selected groups of synchronization signals rather than all possible signals. By applying descrambling to a subset of sequences in multiple passes, the system achieves sufficient detection accuracy with reduced energy expenditure compared to exhaustive processing.
3Productivity
If sequence grouping is implemented, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces a grouping mechanism that divides synchronization sequences into manageable groups. While this adds some structural complexity for group management, it dramatically improves processing efficiency by enabling parallel and staged processing, making the overall system more practical despite the added organizational layer.
Data Source
AI summary
A chip for detecting a synchronization signal generated based on one of a plurality of sequences, which is generated by a sequence generator, the chip including a memory, and a processor connected to the memory may be provided. The processor may be configured to receive the synchronization signal, perform first descrambling the received synchronization signal for a first sequence from among the plurality of sequences by multiplying the received synchronization signal by the first sequence, and perform second descrambling the received synchronization signal for a second sequence, which is a complex conjugate of the first sequence, from among the plurality of sequences of the received synchronization signal by changing a sign of at least one element of a descrambled sequence of the first sequence.