Synchronous Virtual CPU Scheduling via Inter-Processor Interrupts

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Solution Overview

Problem

In existing virtual machine environments, multiple virtual CPUs (VCPUs) belonging to the same Guest Operation System (GOS) do not operate synchronously, leading to timeouts and degraded performance in concurrent program execution due to unsynchronized scheduling, which affects timer operations and inter-thread synchronization.

Innovation Solution

A method and computer system for synchronous scheduling of multiple virtual CPUs, where a second virtual CPU is determined to be synchronously operated with a first virtual CPU, and synchronization requests are transmitted to corresponding physical CPUs to ensure synchronized operation, using inter-processor interrupts for preemptive scheduling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple VCPUs are scheduled independently on different physical CPUs without synchronization, then CPU utilization is improved through parallel execution, but timer timeout problems occur due to unsynchronized clock interrupts

Engineering Contradiction:
ImproveCPU utilizationVSAvoidtimer operation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the VMM monitors the scheduling states of multiple VCPUs and dynamically adjusts their scheduling to maintain synchronization. The system detects when VCPUs are desynchronized and sends synchronization notifications to realign their execution states, ensuring timer operations remain reliable while maintaining high CPU utilization through parallel execution.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The VMM acts as an intermediary between the GOS and physical CPUs, managing the synchronization of multiple VCPUs. It receives clock interrupts from physical CPUs, processes timing information, and coordinates the scheduling of VCPUs to ensure they operate synchronously, thereby preventing timer timeouts while enabling parallel CPU utilization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If multiple VCPUs operate asynchronously to enable concurrent program execution, then execution speed is improved, but concurrent program performance degrades due to lack of synchronization between threads

Engineering Contradiction:
Improveexecution speedVSAvoidconcurrent program performance
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The system uses feedback mechanisms to monitor the execution states of threads running on different VCPUs. When synchronization is required for concurrent programs, the VMM detects the need and coordinates between VCPUs to maintain proper synchronization, ensuring that threads can execute in parallel while still achieving correct synchronization points for inter-thread communication.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The VMM performs preliminary synchronization actions by pre-establishing synchronization mechanisms for concurrent programs before execution begins. It configures the scheduling queues and synchronization protocols in advance, allowing threads to execute concurrently at high speed while knowing that synchronization points are already prepared and coordinated.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If clock interrupts are transmitted only to the VBSP, then system simplicity is maintained, but timeout problems arise when VAP scheduling is not synchronized with VBSP

Engineering Contradiction:
Improveinterrupt transmission complexityVSAvoidtimer timeout
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments the interrupt handling function by separating the reception of clock interrupts (handled by VBSP) from the distribution of timing information to VAPs. The VMM acts as an intermediate segment that receives interrupts from physical CPUs and distributes synchronized timing signals to multiple VCPUs, preventing timeouts without requiring complex changes to the basic interrupt transmission architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The VMM serves as an intermediary between the VBSP and VAPs for timing synchronization. While clock interrupts continue to be transmitted only to the VBSP, the VMM receives these interrupts and generates synchronized timing signals that are distributed to all VAPs, ensuring they remain synchronized with the VBSP without increasing interrupt transmission complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8381210B2Method and computer for synchronous scheduling of multiple virtual CPUs
Publication Date: 2013.02.19 LENOVO SOFTWARE
  • US8381210B2 patent drawing
  • US8381210B2 patent drawing
  • US8381210B2 patent drawing

AI summary

According to the present invention, a method and computer for synchronous scheduling of multiple virtual CPU is provided, which comprises: a guest operation system, comprising a first virtual CPU and a second virtual CPU; a first physical CPU and a second physical CPU; a virtual machine monitor, comprising: synchronous notifying module, for notifying, in a synchronous manner, the second physical CPU corresponding to the second virtual CPU after the second virtual CPU is determined to be synchronously operated with the first virtual CPU scheduled to the first physical CPU; and synchronous scheduling module, for scheduling the second virtual CPU out of the scheduling queue; wherein the second virtual CPU is operated on the second physical CPU. According the above technical solution, the synchronous scheduling of the multiple virtual CPUs belonging to the synchronous GOS can be achieved. The timeout problem in the prior art due to the unsynchronized operation of multiple VCPUs can thus be effectively solved, and the execution performance of the concurrent programs can be improved.