Synchronization Determining Circuit for Serial Receiver Clock
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Solution Overview
Problem
Conventional clock and data recovery (CDR) systems in serial transmission systems, such as USB and PCI-Express, can only determine if the recovery clock frequency is within a reasonable range but fail to accurately confirm whether the recovery clock is synchronized in terms of frequency and phase.
Innovation Solution
A synchronization determining circuit is introduced in the receiver, comprising a comparison unit and a determining unit, which processes serial data to generate comparison signals and synchronization state signals based on reference values from synchronous patterns, allowing for accurate determination of the recovery clock's synchronization state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a crystal clock with fixed frequency is used to measure recovery clock cycles, then the frequency range can be determined, but accurate synchronization confirmation is not achieved
Solution Approach 1:
The patent replaces the mechanical crystal clock-based measurement system with an electronic digital processing system. The synchronization determining circuit uses digital counters and comparators to process the synchronous pattern, substituting the analog crystal clock mechanism with a digital logic-based approach that can accurately determine both frequency and phase synchronization through binary comparison operations.
Solution Approach 2:
The patent introduces a synchronous pattern as an intermediary signal element that mediates between the transmitted clock signal and the recovered clock signal. This synchronous pattern serves as a reference marker that enables the receiver to compare and determine synchronization status without directly relying on crystal clock cycle counting, thus resolving the contradiction between measurement capability and synchronization confirmation reliability.
2Measurement precision
If crystal clock cycle counting is used to determine frequency range, then frequency estimation is possible, but phase synchronization cannot be confirmed
Solution Approach 1:
The patent applies preliminary action by pre-embedding a known synchronous pattern into the transmitted data stream before transmission. This synchronous pattern is processed in advance by the receiver to generate a reference signal that contains both frequency and phase information. By preparing this reference in advance, the system can simultaneously determine both frequency and phase synchronization without losing phase information during the measurement process.
3Device complexity
If a simple cycle counting method is used, then the device complexity is low, but synchronization determination precision is insufficient
Solution Approach 1:
The patent segments the synchronization determination process into distinct functional modules: a synchronous pattern detection unit, a counter unit for frequency measurement, and a comparator unit for phase comparison. This segmentation allows each module to perform a specific function with simple logic, maintaining low overall device complexity while achieving high synchronization determination precision through the coordinated operation of these modular components.
Data Source
AI summary
A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.