Synchronization Logic for Contention in Multi-Core Memory Requests

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Solution Overview

Problem

Modern computer processors with multiple cores face cache coherence issues when multiple threads attempt to modify the same data simultaneously, leading to processing bottlenecks due to the need for blocking cache coherence protocols, which serially process memory requests and result in increased execution time.

Innovation Solution

Incorporating synchronization logic that determines whether memory requests are in contention, using a non-blocking cache coherence protocol to process requests in parallel by sending messages associated with one request before completing the other, thereby reducing overall execution time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If blocking cache coherence protocol is used to maintain cache coherence, then cache coherence is maintained, but memory requests are processed serially resulting in increased execution time

Engineering Contradiction:

Improvecache coherenceVSAvoidexecution time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically switches between blocking and non-blocking cache coherence protocols based on real-time contention detection. When contention is detected among memory requests, the system applies non-blocking protocol to process requests in parallel; when no contention exists, blocking protocol is used. This dynamic adaptation resolves the contradiction by optimizing execution time without compromising cache coherence under different operational conditions.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The synchronization logic changes the processing mode parameter of cache coherence protocol from static (always blocking) to dynamic (blocking or non-blocking based on contention state). By monitoring contention parameters and adjusting the protocol behavior accordingly, the system maintains cache coherence while reducing execution time in contending scenarios.

Inventive Principle:

Principle #35Parameter changes

2Loss of time

If non-blocking cache coherence protocol is used to process memory requests in parallel, then execution time is reduced, but cache coherence may be compromised

Engineering Contradiction:

Improveexecution timeVSAvoidcache coherence

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The synchronization logic acts as an intermediary between memory requests and the cache coherence protocol. It detects contention among requests and selectively applies non-blocking protocol only when appropriate, while ensuring cache coherence is maintained through proper synchronization. This intermediary control mechanism enables parallel processing without compromising reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback through contention detection logic that monitors memory request states. Based on this feedback, the system determines whether to apply blocking or non-blocking protocol, ensuring that cache coherence is maintained while optimizing execution time. The feedback loop continuously adjusts protocol selection based on current system state.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10430252B2Synchronization logic for memory requests

Publication Date: 2019.10.01 INTEL CORP

AI summary

In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory request and a second memory request; determine whether the second memory request is in contention with the first memory request; and in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol. Other embodiments are described and claimed.