Synchronized Multi-Frequency Clock Generation With Shared DCO Control
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Solution Overview
Problem
Existing clock generators face challenges in minimizing cost, power consumption, circuitry dimensions, complexity, and jitter while maximizing functionality, performance, and reliability, particularly in generating multiple clocks with synchronized phase relationships.
Innovation Solution
A multiple frequency clock generator comprising an independent digital control oscillator (DCO) and a dependent DCO, along with a delay lock loop (DLL) and phase lock loop (PLL), which aligns clocks at their common multiple frequency with or without adjustment, using tap select signals to maintain desired phase and frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple independent clock generators are used to generate multiple clocks, then each clock can be generated independently, but the circuitry complexity and cost increase
Solution Approach 1:
The system segments clock generation into an independent DCO that generates a master clock and dependent DCOs that generate slave clocks from the master clock. This segmentation allows independent control of the master clock while deriving multiple slave clocks through a shared architecture, reducing overall circuitry complexity compared to completely independent generators.
Solution Approach 2:
The delay lock loop (DLL) and tap select signal mechanism serve multiple functions: they enable frequency multiplication, phase adjustment, and clock distribution to multiple dependent DCOs. This multi-functionality reduces the need for separate circuitry for each clock generation task, thereby reducing overall device complexity.
2Adaptability or versatility
If multiple independent clock generators are used to generate multiple clocks, then each clock can be generated independently, but the cost increases
Solution Approach 1:
The shared DLL and tap select signal architecture performs multiple functions (frequency multiplication, phase adjustment, clock distribution) that would otherwise require separate circuits, reducing component count and manufacturing cost while maintaining the ability to generate multiple independent clocks.
Solution Approach 2:
Multiple dependent DCOs share the same DLL and clock source infrastructure, merging common functions into a single shared architecture. This consolidation reduces redundant components and lowers overall system cost compared to completely independent clock generators.
3Adaptability or versatility
If traditional clock generators are used to generate multiple clocks, then functionality is provided, but phase synchronization between clocks is difficult to maintain
Solution Approach 1:
The system uses feedback mechanisms where dependent DCOs receive tap select signals from the independent DCO and adjust their operation accordingly. This feedback loop ensures that phase and frequency adjustments made to the master clock are propagated to slave clocks, maintaining phase synchronization across all generated clocks.
Solution Approach 2:
The DLL pre-adjusts the phase and frequency of the master clock signal before distributing it to dependent DCOs through tap select signals. This preliminary action ensures that phase synchronization is established in advance, making it easier to maintain synchronized operation across multiple clocks.
4Adaptability or versatility
If multiple independent clock generators are used, then each clock can operate independently, but power consumption increases
Solution Approach 1:
The shared DLL and tap select signal architecture provides multiple functions (frequency control, phase adjustment, clock distribution) through a single infrastructure, eliminating the need for separate power-consuming circuits in each independent clock generator while maintaining independent operation capability.
Solution Approach 2:
Multiple dependent DCOs share the same clock source and control infrastructure, merging power-consuming functions into a single shared system. This consolidation reduces total power consumption compared to running multiple completely independent clock generators, while still allowing independent clock operation through the tap select mechanism.
Data Source
AI summary
Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.