Synchronized Count Value Generation Across Variable Clock Domains
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Solution Overview
Problem
In data processing systems with varying clock frequency domains, generating consistent timestamps is challenging due to differing clock frequencies, and high-frequency clocks required for high resolution consume significant power, making it difficult to provide timestamp information efficiently across the system.
Innovation Solution
A count value generator that uses a slower synchronizing count value to synchronize between domains, with a local clock providing higher resolution lower order bits, determined by calculating the frequency ratio between the local and synchronizing frequencies, allowing for efficient power usage and adaptability to frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-frequency clock signal is used to generate high-resolution timestamps, then timestamp resolution is improved, but power consumption increases significantly
Solution Approach 1:
The timestamp is segmented into two parts: high-order bits generated by a low-frequency counter (power-efficient) and low-order bits generated by a high-frequency counter (high resolution). This segmentation allows the system to achieve high-resolution timestamps without continuously operating high-frequency clocks, thereby reducing power consumption while maintaining measurement precision.
2Adaptability or versatility
If different clock frequency domains are used in data processing systems, then system flexibility and performance are improved, but timestamp consistency across domains becomes difficult to maintain
Solution Approach 1:
A synchronisation counter operating at a defined synchronisation frequency acts as an intermediary between different clock frequency domains. This synchronisation counter provides a common reference that allows timestamps from different clock domains to be correlated and maintained consistently across the system, while still allowing each domain to operate at its optimal frequency for performance and flexibility.
Data Source
AI summary
A count value generator includes an input for receiving a synchronizing count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronizing frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronizing frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronizing count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.