Synchronized Debug Exit in Multi-Processor SoC Systems
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Solution Overview
Problem
Existing multi-processor system-on-a-chip (SoC) debugging methods are complex and inefficient, particularly in synchronously exiting debug mode, due to varying instruction lengths and sequences for different units, complicating the reactivation process.
Innovation Solution
A modified GO+EXIT TAP instruction is introduced, which is treated as a no-operation (NOP) by processors not in debug mode, allowing all processors to assert a debug exit signal and exit debug mode synchronously, simplifying the reactivation process by broadcasting a single instruction across all processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If individual units enter debug mode at varying times and are reactivated individually, then each unit can be debugged separately, but the reactivation process becomes complex and time-consuming
Solution Approach 1:
The patent combines multiple individual reactivation operations into a single synchronized reactivation event. The top-level TAP controller coordinates all processor cores to exit debug mode simultaneously using a common GO+EXIT signal, eliminating the need for separate reactivation sequences for each core.
Solution Approach 2:
The patent creates a universal reactivation mechanism that works for any combination of processor cores in debug mode. The synchronized exit approach provides a single method that handles all possible scenarios (one core, multiple cores, all cores) without requiring different reactivation procedures.
2Productivity
If a single long pseudo-instruction is formed to control all halted units, then all units can be reactivated through one sequence, but the instruction formation becomes extremely complex
Solution Approach 1:
The patent segments the reactivation control into two independent parts: (1) a simple GO+EXIT instruction that is broadcast to all processors, and (2) individual processor responses to that instruction. This eliminates the need to form a single complex pseudo-instruction while maintaining synchronized reactivation.
Solution Approach 2:
The patent introduces the GO+EXIT instruction as an intermediary signal that mediates between the external debugger and multiple processor cores. This single instruction serves as a universal trigger that all processors recognize and respond to uniformly, simplifying the control mechanism.
3Adaptability or versatility
If TAP controllers are linked in serial fashion for debugging, then individual units can be accessed separately, but the linking control information becomes complicated for any combination of units
Solution Approach 1:
The patent inverts the traditional serial linking approach by using parallel broadcasting for the critical reactivation function. Instead of sending different instructions through a serial chain to each processor, the system broadcasts a single GO+EXIT instruction to all processors simultaneously, reversing the control flow direction.
Data Source
AI summary
A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.