Synchronized Execution Partitions for High Availability Failover

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Solution Overview

Problem

High availability computer systems face challenges in minimizing downtime due to processor failures, where existing solutions either lead to significant performance degradation or are costly and inefficient, and existing methods for software failures often require physical intervention or lengthy recovery times.

Innovation Solution

A method for synchronized execution of applications in a high availability environment involving configuration of modules into execution partitions with a control partition for error logging and failover, allowing for seamless transition to a degraded mode and dynamic reconfiguration without service interruption, utilizing a high-speed network for synchronization and error handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hardware redundancy is used to improve processor resilience, then system availability is improved, but cost increases

Engineering Contradiction:
Improveprocessor resilienceVSAvoidcost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent creates a secondary processor that copies the execution state and data from the primary processor. This copy mechanism allows for failover without requiring complete hardware redundancy, reducing cost while maintaining resilience. The secondary processor maintains a synchronized state through memory copying and instruction streaming.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The system performs preliminary synchronization of the secondary processor with the primary processor before failures occur. By continuously copying memory states and pre-synchronizing execution contexts, the system prepares the backup in advance, enabling rapid failover without requiring full hardware redundancy upfront.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If processor card replacement is performed to restore service after failure, then system resilience is improved, but service interruption time increases

Engineering Contradiction:
Improvesystem resilienceVSAvoidservice interruption time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The secondary processor is pre-configured and continuously synchronized with the primary processor before failures occur. This preliminary preparation allows the system to switch to the secondary processor immediately upon failure detection, eliminating the need for time-consuming processor card replacement and reducing service interruption time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system performs automatic failover from the primary to secondary processor when failures are detected, without requiring manual intervention for processor replacement. The hot-swapping capability allows the faulty processor to be replaced while the system continues operating on the secondary processor, enabling self-service recovery.

Inventive Principle:
Principle #25Self-service

3Reliability

If data migration is performed before processor replacement, then system resilience is improved, but recovery duration increases

Engineering Contradiction:
Improvesystem resilienceVSAvoidrecovery duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The secondary processor continuously receives and applies memory copy operations and instruction streams from the primary processor during normal operation. This preliminary data synchronization ensures that when failover occurs, the secondary processor already has the necessary data in its memory, eliminating the need for time-consuming data migration during recovery.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system maintains continuous data synchronization between primary and secondary processors through ongoing memory copy operations and instruction streaming. This continuous useful action ensures data consistency is maintained throughout operation, allowing immediate resumption of service after failover without interruption for data migration.

Inventive Principle:
Principle #20Continuity of useful action

4Reliability

If synchronization of primary and secondary processors is maintained, then failover capability is improved, but system complexity increases

Engineering Contradiction:
Improvefailover capabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a memory management unit and instruction stream mechanism as intermediaries to manage synchronization between primary and secondary processors. These intermediary components handle the complex tasks of memory copying, state synchronization, and instruction coordination, simplifying the overall control logic while maintaining reliable failover capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2975517B1Method and device for synchronised execution of an application in a high-availability environment
Publication Date: 2021.12.08 BULL SA
  • EP2975517B1 patent drawingFigure 1~2
  • EP2975517B1 patent drawingFigure 3~4
  • EP2975517B1 patent drawingFigure 5

AI summary

The present invention relates essentially to a method for the synchronized execution of an application in a high-availability environment comprising a plurality of computing modules interconnected by a very high-speed network, characterized in that it comprises the following steps: - configuration (2000) of the plurality of modules into a plurality of partitions, including at least: o two execution partitions, one primary and the other secondary o one control partition; - execution (2100) of the application on each execution partition, with the input/output processed by the primary partition being transmitted to the secondary execution partition via the control partition; - synchronization (2200) of the executions via exploitation of microprocessor context changes; - transmission (2300) of a catastrophic error signal to the control partition;- continuation (2500) of execution by switching to a degraded mode, execution continuing on a single partition.;