Synchronized I/Q Detection Circuit for Fast Phase Settling
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Solution Overview
Problem
Conventional I/Q phase detection circuits suffer from slow detection times and low accuracy due to reliance on low bandwidth resistor-capacitor (RC) filters and process variation issues, leading to incomplete settling and voltage ripple problems.
Innovation Solution
A synchronized I/Q detection circuit is introduced, featuring reset and sampling circuits synchronized with phase detectors to cancel settling issues and improve power efficiency, utilizing multiplexers and control signal generators to manage input signals and reset/sampling signals for faster phase detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low bandwidth RC filters are used to extract DC values from phase-detector, then filtering performance is improved, but detection time increases and accuracy decreases
Solution Approach 1:
The patent extracts only the essential DC component information from the phase-detector output using synchronized sampling at specific time points, rather than using bandwidth-limited RC filters. This extraction approach removes the time-consuming filtering process while retaining the necessary phase difference information.
Solution Approach 2:
The patent performs preliminary synchronization of the sampling operation with the phase-detector output waveform, capturing samples at predetermined time points before any filtering would occur. This preliminary sampling action eliminates the need for subsequent low-bandwidth filtering, thereby reducing detection time while maintaining accuracy.
2Reliability
If low bandwidth RC filters are used to extract DC values, then filtering performance is improved, but measurement precision deteriorates
Solution Approach 1:
The sampling operation is preliminarily synchronized with the phase-detector output waveform, capturing voltage samples at specific time points where the waveform characteristics are known. This preliminary sampling at optimized time points provides accurate phase difference measurement without the distortion introduced by low-bandwidth RC filtering.
Solution Approach 2:
The patent changes the operational parameters from continuous low-bandwidth filtering to discrete synchronized sampling at specific time points. This parameter change allows capturing the essential phase information with higher precision by sampling at optimal moments in the waveform cycle, avoiding the bandwidth-induced accuracy loss.
3Device complexity
If conventional phase detection circuits are used, then implementation is simplified, but detection accuracy decreases due to process variation
Solution Approach 1:
The patent implements preliminary synchronization of the sampling operation with the phase-detector output, capturing samples at predetermined time points that are synchronized with the waveform. This preliminary timing synchronization compensates for process variations by consistently sampling at the same phase points, improving measurement precision while keeping the circuit implementation relatively simple.
4Loss of time
If synchronized sampling is implemented, then settling time is reduced, but power consumption increases
Solution Approach 1:
The patent employs periodic sampling at specific time points synchronized with the phase-detector output waveform, rather than continuous operation. This periodic action reduces power consumption by activating the sampling and processing circuits only when needed, while still achieving fast settling by capturing the essential information at synchronized moments.
Solution Approach 2:
The patent performs partial sampling by capturing voltage samples at specific predetermined time points rather than continuously processing the entire waveform. This partial action approach reduces power consumption by limiting processing to only the necessary sampling moments, while the synchronized timing ensures that the captured samples are sufficient for accurate phase detection with fast settling.
Data Source
AI summary
A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.