Synchronized MMUs for Scalable Multi-Dielet GPU Memory Management

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The physical limitations of packing an increasing number of components on a single semiconductor die in GPUs lead to heat management, interconnect challenges, and signal issues, while growing workload demands exceed these limits, necessitating a scalable solution beyond a single die.

Innovation Solution

A multi-dielet processing system is introduced, where multiple dies are interconnected to form a larger GPU, with synchronized memory management units (MMUs) presenting a unified logical MMU to software, allowing for efficient memory access and protection across dielets, and enabling a monolithic view of the system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If more components are packed on a single die, then processing capacity and functionality are improved, but heat management and interconnect reliability deteriorate

Engineering Contradiction:
Improveprocessing capacityVSAvoidheat management
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The system divides the GPU into multiple separate dies (dielets), each containing a portion of the processing components. This segmentation allows heat to be distributed across multiple physical packages rather than concentrated on a single die, while the interconnect fabric enables the segmented units to function as a unified high-capacity processor.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If more components are packed on a single die, then functionality is improved, but interconnect difficulty and signal issues worsen

Engineering Contradiction:
ImprovefunctionalityVSAvoidinterconnect difficulty
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Instead of increasing component density on a two-dimensional die surface, the system adds a third dimension by stacking multiple dies vertically and connecting them through an interconnect fabric. This dimensional transition allows complex functionality to be achieved without the signal integrity and routing challenges associated with high-density single-die interconnects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If multiple dies are used to expand processing capacity, then scalability is improved, but memory management complexity worsens

Engineering Contradiction:
Improveprocessing capacityVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system merges multiple distributed memory management units into a unified logical MMU through synchronization mechanisms. This allows the multi-die system to present a single, coherent memory management interface to software, eliminating the need for complex distributed memory management while maintaining scalability across multiple dies.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

A synchronization mechanism acts as an intermediary between the distributed MMUs on different dies, coordinating memory management operations and presenting a unified interface. This intermediary layer abstracts the complexity of distributed memory management from both software and individual die operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Adaptability or versatility

If a multi-dielet architecture is implemented, then scalability beyond physical limits is improved, but software compatibility and synchronization complexity worsen

Engineering Contradiction:
ImprovescalabilityVSAvoidsynchronization complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The synchronized MMU architecture provides a universal interface that is compatible with existing software while supporting multi-dielet configurations. The system can function as either a single unified GPU or as multiple independent GPUs, providing versatility without requiring software customization while managing synchronization internally.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12524350B2Synchronizing memory management units in multi-dielet processor architectures
Publication Date: 2026.01.13 NVIDIA CORP
  • US12524350B2 patent drawing
  • US12524350B2 patent drawing
  • US12524350B2 patent drawing

AI summary

This disclosure describes supporting distributed graphics and compute engines in a multi-dielet parallel processing system, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronizing memory management in such architectures. Respective dielets each has a memory management unit (MMU). The processing of at least one memory-related message type is serialized by a designated MMU for messages originated at any dielet, and the processing of at least some memory-related message types is performed locally on the originating dielets.