Synchronized NIC Hold-and-Release for Fair Packet Delivery

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Solution Overview

Problem

Current fair data packet delivery systems experience delay variance due to non-identical and dynamic pathing, hardware variations, and software-based synchronization issues, leading to inconsistent packet delivery times across receivers.

Innovation Solution

Implementing a hold-and-release mechanism using network interface controllers (NICs) with synchronized hardware clocks to ensure data packets are delivered within tens of nanoseconds of each other, eliminating software-based jitter and system-specific delay variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based packet delivery is used, then implementation flexibility is improved, but delay variance and jitter increase

Engineering Contradiction:
Improveimplementation flexibilityVSAvoidpacket delivery timing precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent replaces software-based packet timing control with hardware-based timing control using NICs with synchronized clocks. The hardware timing mechanism eliminates the jitter and delay variance inherent in software-based approaches while maintaining implementation flexibility through standardized network interface controllers.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces NICs with synchronized hardware clocks as intermediary devices between the packet source and receivers. These intermediaries provide precise timing control and buffer packets to ensure simultaneous delivery, resolving the timing precision issues without requiring complex software synchronization protocols.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If hardware pacing or rate limiting is applied at packet egress, then network traffic congestion is reduced, but packet delivery fairness deteriorates

Engineering Contradiction:
Improvenetwork throughputVSAvoidpacket arrival time consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Instead of applying pacing at packet egress (output side), the patent applies timing control at packet ingress (input side). By synchronizing clocks at the receiving NICs and buffering packets upon receipt, the system ensures simultaneous delivery without the need for egress-side rate limiting, thus maintaining both throughput and fairness.

Inventive Principle:
Principle #13The other way round (Inversion)

3Adaptability or versatility

If non-identical dynamic pathing is used for packets, then system adaptability is improved, but delay variance increases

Engineering Contradiction:
Improvepath routing flexibilityVSAvoidpacket arrival time consistency
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent creates an equipotential timing environment by synchronizing the clocks of all NICs to a common time reference. This ensures that regardless of the dynamic paths packets take through the network, all receivers operate on the same time baseline, allowing for fair simultaneous delivery despite path variations.

Inventive Principle:
Principle #12Equipotentiality

Data Source

PatentEP4586583A1Fair data packet delivery on computing platforms
Publication Date: 2025.07.16 GOOGLE LLC
  • EP4586583A1 patent drawingFigure 1
  • EP4586583A1 patent drawingFigure 2
  • EP4586583A1 patent drawingFigure 3

AI summary

Methods, systems, and apparatus are provided for fair data packet delivery. In some applications, such as financial exchanges, online gaming, and consensus protocols, having data received by each receiver at or near the same time can be just as important, if not more important, than achieving minimal latency. A system as described herein implements a hold- and-release of data packets on network interface controllers to ensure data packets are delivered to multiple receivers within tens of nanoseconds of one another. The system described can be implemented on a variety of different network devices with different built-in traffic shaping functionality. The hold and release is achieved by precise clocks in hardware, synchronized to deliver packets in a manner that reduces latency variation introduced in other end-to-end packet delivery systems. A fair data packet delivery system is achieved without relying on either software and its associated jitter, or system-specific notions of fairness.