Synchronized PWM Control Boards for Lower DC-Link Ripple
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Solution Overview
Problem
Existing pulse width modulation systems face challenges in achieving even power outtake over time due to hard synchronization methods, leading to issues such as large capacitor voltage variations and DC link ripples, particularly in silicon carbide-equipped traction converters used in railway applications.
Innovation Solution
A pulse width modulation system employing soft synchronization between control modules, where slave control boards determine a fictive master board timer based on communication bus information, synchronizing their timer rates and interlacing angles to minimize variations in operation parameters, such as capacitor voltage and DC-link ripples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard synchronization is applied to synchronize control boards, then timer synchronization is achieved, but control boards must be restarted in a certain order and interrupt handling becomes complex
Solution Approach 1:
The patent introduces a master control board as an intermediary that centralizes timer management. Slave control boards receive synchronization signals from the master board through a communication bus, eliminating the need for complex distributed interrupt handling while maintaining timer synchronization across all control boards
Solution Approach 2:
The patent changes the synchronization parameter from shared timer values (hard synchronization) to synchronized timer rates with offset compensation (soft synchronization). Each slave board maintains its own timer but adjusts its timer rate and adds an offset value based on messages from the master board, achieving synchronization without the complexity of coordinated restarts and interrupt handling
2Ease of operation
If loads are controlled without interlacing, then control simplicity is maintained, but power outtake is not even over time causing large capacitor voltage variations
Solution Approach 1:
The patent implements periodic interlacing of load control where slave control boards receive interlacing angle information from the master board and adjust their PWM output timing accordingly. This periodic coordination ensures that loads connected to different control boards are controlled in an interleaved manner, distributing power outtake evenly over time and reducing capacitor voltage variations
Solution Approach 2:
The master control board sends interlacing angle information to slave control boards based on timer information received via the communication bus. This feedback mechanism enables slave boards to adjust their control timing dynamically, achieving even power distribution while maintaining operational simplicity through centralized coordination
3Loss of energy
If SiC modules are used to reduce losses, then energy efficiency improves, but the relative size of DC-link capacitor increases
Solution Approach 1:
The patent applies periodic interlacing control to SiC-based PWM modules, where the master control board coordinates timing offsets among slave boards. This interlacing strategy smooths power outtake variations, reducing the ripple current that the DC-link capacitor must handle, thereby allowing for a smaller capacitor size even in high-efficiency SiC modules
Solution Approach 2:
The patent changes the control parameter from uniform timing to offset-based interlaced timing. By adjusting the timer rate and adding offset values as received from the master board, slave boards create an interleaved PWM pattern that reduces peak current demands and capacitor stress, enabling reduced capacitor size in SiC applications
Data Source
AI summary
A pulse width modulation system includes a plurality of module building blocks One control board is a master control board and others are slave control boards. Each slave control board determines a fictive master board timer based upon timer information received via a communication bus, and synchronizes the timer rate of a slave board timer to a timer rate of the master control board, or of an external timer rate. The timer information includes interlacing angle information defining an interlacing point for each of the control boards receiving the timer information. The interlacing angles are determined in relation to each other such that variation of a predetermined operation parameter, related to loads connected to pulse width modulated phase outputs of function modules, is minimized. At least two control boards, for which the interlacing angles are determined, are arranged to control function modules at different module building blocks.