Synchronized Reset for Circuit Emulator FPGAs
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Solution Overview
Problem
Existing circuit emulation systems face challenges in synchronizing reset signals across multiple field-programmable gate arrays (FPGAs) during massively parallel computation, particularly in emulating multiple netlists for multiple clients, leading to asynchronous and insecure emulation tests.
Innovation Solution
A computer-implemented method and system that provide a reset message with a selected clock cycle to multiple circuits, determining a mask for each circuit, and tuning the reset signal relative to the clock signal to ensure synchronized assertion of the reset signal across FPGAs, using precise cabling and connectors to maintain timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple FPGAs are used to emulate multiple netlists in parallel, then the emulation capacity and productivity are improved, but the synchronization of reset signals across FPGAs deteriorates
Solution Approach 1:
The system segments the emulation workload across multiple FPGAs, with each FPGA handling a specific netlist or portion thereof. The reset signal is similarly segmented and distributed to each FPGA individually through dedicated pathways, allowing parallel operation while maintaining independent control over reset timing for each segment.
Solution Approach 2:
A central controller or intermediary device is introduced to manage reset signal distribution across multiple FPGAs. This intermediary receives a single reset source and generates synchronized reset signals for each FPGA based on their specific clock cycles and emulation schedules, acting as a mediator that coordinates the distributed system.
2Reliability
If reset signals are provided to multiple FPGAs simultaneously, then the emulation test coverage is improved, but the timing precision and security of reset assertion deteriorates
Solution Approach 1:
Each FPGA receives a customized reset signal configuration tailored to its specific requirements, including netlist complexity, clock frequency, and emulation schedule. The reset signal parameters (timing, duration, assertion level) are locally optimized for each FPGA rather than using a uniform approach, ensuring precise timing control while maintaining comprehensive test coverage.
Solution Approach 2:
The system performs preliminary analysis of each netlist and FPGA configuration to determine optimal reset timing parameters before emulation begins. Reset schedules and timing masks are pre-calculated and stored, allowing the system to assert reset signals at precisely the right moments for each FPGA without real-time computation delays.
3Adaptability or versatility
If independent netlists are emulated on multiple clients, then the versatility and adaptability are improved, but the ability to perform securely separated emulation tests deteriorates
Solution Approach 1:
The system segments both the netlists and client access across multiple FPGAs, with each FPGA assigned to specific clients and netlists. This segmentation creates natural security boundaries where clients can only access their designated FPGAs and netlists, preventing unauthorized cross-access while maintaining high versatility in supporting multiple independent emulation scenarios.
Solution Approach 2:
Each FPGA is configured with local security policies and access controls specific to its assigned clients and netlists. The reset signal distribution mechanism incorporates client-specific masks that enable or disable reset assertion based on authorized client operations, ensuring that security separation is maintained at the local level for each client-FPGA pair.
Data Source
AI summary
A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.