Synchronized Time-to-Digital Converter for Coarse-Fine Code Accuracy
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Solution Overview
Problem
Existing time to digital converters suffer from reduced conversion accuracy due to code errors in the connection between coarse and fine TDC data, particularly when the timing transitions are close and operational delays occur.
Innovation Solution
A time to digital converter system with a synchronized circuit design that includes a fine TDC, coarse TDC, and a synchronization circuit, utilizing multiphase phase locked loops and Gray codes to accurately convert time intervals into digital signals, even in the presence of operational delays and degraded clock signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If coarse TDC and fine TDC are used together for time interval measurement, then measurement range is improved, but conversion accuracy deteriorates due to code errors in connection between coarse and fine TDC data
Solution Approach 1:
A synchronization circuit is introduced as an intermediary between the fine TDC and coarse TDC. This circuit includes a timing signal generation unit that generates timing signals based on the fine TDC output, and a synchronization signal generation unit that creates synchronization signals for the coarse TDC. This intermediary ensures proper coordination between the two TDCs, eliminating code errors in their connection while maintaining extended measurement range.
2Measurement precision
If timing transitions are close together, then measurement resolution is improved, but operational delays cause code errors that reduce conversion accuracy
Solution Approach 1:
The synchronization circuit performs preliminary actions by generating timing signals and synchronization signals before the coarse TDC processes the time interval data. The timing signal generation unit creates precisely timed signals in advance, and the synchronization signal generation unit prepares coordination signals beforehand, ensuring that even when timing transitions are close together, the coarse TDC receives properly synchronized inputs without code errors.
3Measurement precision
If multiphase phase locked loops are used for time to digital conversion, then measurement capability is improved, but signal level instability and operational delays reduce conversion accuracy
Solution Approach 1:
The synchronization circuit implements feedback mechanisms where the timing signal generation unit continuously monitors and adjusts timing signals based on the fine TDC output, and the synchronization signal generation unit adjusts synchronization signals for the coarse TDC based on observed timing relationships. This feedback ensures stable signal levels and compensates for operational delays, maintaining high measurement capability while improving signal stability.
Data Source
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AI summary
Provided is a time to digital converter that outputs time interval digital data having multiple bits according to a time interval from a first timing to a second timing, the time to digital converter including a first circuit configured to generate lower order bits among the multiple bits, a second circuit configured to generate higher order bits among the multiple bits, and a third circuit configured to synchronize the first circuit and the second circuit by generating a second signal with use of a first signal output from the first circuit and outputting the second signal to the second circuit, in which the first signal is generated by using a signal with multiple bits among the lower order bits.