Synchronized Multi-Directional Transfer for Inter-Processor Power Management
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Solution Overview
Problem
Existing PCIe technologies consume significant electrical power and lack effective power management infrastructure, making them unsuitable for portable consumer electronics where power conservation is critical, as they do not consider power saving states during transactions, leading to unnecessary power state transitions and increased energy consumption.
Innovation Solution
Implementing a synchronized multi-directional transfer mechanism on an inter-processor communication link that allows processors to remain in low power states for longer, reduces transitions between power states, and minimizes interrupts, by using a physical bus interface to accumulate and transfer data during synchronization frames, thereby optimizing power management and data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional PCIe technology is used for inter-processor communication, then data transfer capability is provided, but electrical power consumption is significant and power management infrastructure is lacking
Solution Approach 1:
The patent implements periodic synchronization frames that wake the physical bus interface from sleep state at regular intervals to perform data transfers. This periodic activation allows the system to maintain data transfer capability while spending most time in low-power state, directly resolving the contradiction between power consumption and data transfer capability
Solution Approach 2:
Data is accumulated in buffers during low-power states before the synchronization frame wakes the interface. This preliminary accumulation allows bulk transfers to occur efficiently during brief active periods, maintaining productivity while minimizing the duration of high-power states
2Productivity
If processors frequently transition between power states to handle data transfers, then data throughput is maintained, but unnecessary power state transitions increase energy consumption
Solution Approach 1:
Data is pre-accumulated in buffers during low-power states before transfer is needed. This allows the system to remain in low-power state longer and perform bulk transfers during synchronization frames, reducing the frequency of power state transitions while maintaining data throughput
Solution Approach 2:
Data accumulation continues in buffers during low-power states without interruption, maintaining the readiness for transfer. This continuous preparation eliminates gaps in useful action and reduces the need for frequent wake-sleep cycles
3Ease of operation
If PCIe technology operates without considering power saving states, then simple transaction handling is achieved, but unnecessary power state transitions occur
Solution Approach 1:
The synchronization frame mechanism provides a structured periodic schedule for waking the interface from sleep state. This periodic approach maintains simple transaction handling within each active frame while systematically avoiding unnecessary transitions by keeping the interface asleep between frames
Solution Approach 2:
The system automatically manages power state transitions based on the synchronization frame schedule and buffer status, without requiring complex external control. This self-managed approach maintains operational simplicity while eliminating unnecessary transitions through automated sleep-wake scheduling
Data Source
AI summary
Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.