Synchronizer Circuit for Multi-Clock Domain Data Transfer
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Solution Overview
Problem
In IC designs with multiple clock domains, existing synchronizers assume the destination circuit clock is always running, leading to potential malfunctions when the destination clock is off, as they propagate stale signals upon restart, which can result in invalid timestamp values and functional issues.
Innovation Solution
Implementing a synchronizer that detects the destination circuit clock state and uses stop and start signals to clamp and unclamp data signals, ensuring data propagation only when the destination clock is available, thereby preventing stale signal propagation and maintaining clock synchronization even when the destination clock is off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing synchronizers are used to transfer data signals between circuits with multiple clock domains, then data transmission between clock domains is achieved, but stale signals are propagated when the destination clock is off, causing functional malfunctions
Solution Approach 1:
The synchronizer circuit receives feedback signals (stop signal and start signal) from the destination circuit about its clock state. The stop signal is generated when the destination clock is off, and the start signal is generated when the destination clock is on. This feedback mechanism allows the synchronizer to adapt its behavior based on the real-time state of the destination clock, preventing stale signal propagation while maintaining reliable data transmission.
Solution Approach 2:
The synchronizer circuit dynamically adjusts its operation based on the destination clock state. When the destination clock is off, the synchronizer blocks data transmission by generating a stop signal. When the destination clock is on, the synchronizer allows data transmission by generating a start signal. This dynamic adaptation ensures that the synchronizer responds appropriately to changing clock conditions, eliminating the harmful effect of stale signal propagation.
2Reliability
If the synchronizer continuously monitors and controls data transmission based on clock state, then stale signal propagation is prevented, but the device complexity increases
Solution Approach 1:
The synchronizer circuit acts as an intermediary between the source circuit and the destination circuit. It receives data signals from the source circuit and control signals (stop and start signals) from the destination circuit. The synchronizer processes these signals and selectively passes data to the destination circuit based on clock state. This intermediary role allows the synchronizer to manage complexity centrally, coordinating data transmission without requiring complex distributed control throughout the entire system.
Data Source
AI summary
A method and system are provided for synchronizing signals, using a synchronizer circuit, between a source circuit and a destination circuit that utilizes detection of when the destination circuit clock is turned off. In the method performed by the synchronizer circuit, a stop signal is received from the destination circuit that is generated upon determination that the destination clock in the destination circuit is turned off. A data signal from the source circuit is, upon receipt of the stop signal, prevented by the synchronizer circuit from being transmitted from the source circuit to the destination circuit. Then once a start signal is received in response to the destination circuit clock signal turning back on, the data signal is once again transmitted from the source circuit to the destination circuit by the synchronizer.