Synchronizing Circuit for Cross-Domain Data Signal Timing
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Solution Overview
Problem
Conventional data synchronization techniques face challenges in synchronizing data between domains with different local clock frequencies, leading to pulse edge distortion, increased bit error rates, and manufacturing complexities due to differing clock frequencies among processing chips from various manufacturers.
Innovation Solution
A synchronizing circuit that compares positive and negative transitions of the core clock signal with the source clock signal to generate a final sampling signal, allowing data to be sampled and synchronized with the core clock, thereby reducing bit error rates and manufacturing difficulties by deserializing the data stream into multiple parallel streams and synchronizing them with a deserialized source clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred between clock domains with different frequencies, then data transmission is enabled, but pulse edge distortion increases and bit error rate increases
Solution Approach 1:
The patent introduces an intermediary synchronization circuit that includes a phase detector and timing recovery circuit. This intermediary component mediates between the source clock domain and core clock domain, extracting timing information from the transferred data to generate synchronized sampling clocks, thereby reducing pulse edge distortion and bit error rate during cross-domain data transmission
Solution Approach 2:
The patent implements feedback through a timing recovery circuit that continuously monitors the transferred data stream and adjusts the sampling clock phase accordingly. The phase detector compares the incoming data transitions with the sampling clock and feeds back timing correction signals to maintain optimal sampling timing, thereby minimizing bit errors despite clock frequency differences
2Reliability
If PLL circuits are used for clock extraction, then data synchronization is achieved, but chip area occupation increases and noise sensitivity increases
Solution Approach 1:
The patent extracts only the essential timing information from the transferred data stream using a simplified phase detector and timing recovery circuit, rather than implementing a full PLL circuit. This extraction approach achieves the necessary synchronization functionality while occupying significantly less chip area and reducing noise sensitivity by eliminating unnecessary PLL components
3Device complexity
If clock frequencies are matched across domains, then synchronization is simplified, but manufacturing flexibility and adaptability decrease
Solution Approach 1:
The patent employs dynamic timing recovery that automatically adapts to different clock frequency ratios between source and core domains. The phase detector and sampling clock generator dynamically adjust their operation based on the actual frequency relationship, enabling the system to handle various manufacturing scenarios and clock domain configurations without requiring fixed frequency matching
4Adaptability or versatility
If data is transferred over long distances, then domain separation is achieved, but pulse edge distortion increases significantly
Solution Approach 1:
The patent performs preliminary timing recovery and synchronization setup before actual data sampling occurs. The timing recovery circuit pre-adjusts the sampling clock phase based on initial detection of the data stream characteristics, preparing the system in advance to handle long-distance transmission effects and minimize pulse edge distortion during the actual data transfer
Data Source
AI summary
The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling. Also disclosed is a method of synchronizing a data stream, and a data transfer assembly incorporating the synchronization circuit and the method.