Synchronous ADC Circuit for Balanced Voltage and Current Timing
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Solution Overview
Problem
In battery measurement systems, existing technologies face challenges in achieving synchronous analog to digital conversion of battery voltage and current due to time delays introduced by anti-aliasing filters in signal conditioning circuits, which can result in loss of data during high current events and inefficiencies in power consumption states.
Innovation Solution
A synchronous analog to digital conversion system with balanced time delays across signal conditioning circuits, featuring synchronized ADCs and signal conditioning circuits with gains differing by an order of magnitude, integrated into a single package, along with an ADC synchronizing circuit and buffer storage for simultaneous retrieval of voltage and current measurements, enabling precise and simultaneous measurement of battery parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If anti-aliasing filters are added to the ADC input to limit aliasing of high-frequency signals, then signal quality is improved, but time delay in the signal path increases, affecting synchronicity of measured signals
Solution Approach 1:
The signal conditioning circuits are segmented into separate paths for voltage and current measurements, each with its own anti-aliasing filter. By designing these paths independently with matched delay characteristics, the system achieves both high signal quality and synchronized timing without requiring a single complex filtering solution that would introduce excessive delay.
2Adaptability or versatility
If signal conditioning circuits with different gains are used to accommodate varying signal amplitudes, then adaptability is improved, but achieving balanced time delays becomes more difficult, affecting simultaneity of measurement
Solution Approach 1:
The system changes the gain parameter of signal conditioning circuits to accommodate varying signal amplitudes. By carefully selecting and matching the delay characteristics of each conditioning circuit path, the invention achieves both wide adaptability in signal amplitude handling and balanced time delays for synchronous measurement.
3Adaptability or versatility
If the processor is busy servicing other tasks such as communication protocols, then system functionality is improved, but ADC conversions may be missed, resulting in loss of battery state information
Solution Approach 1:
The system performs ADC conversions and prepares measurement data in advance, storing results in buffer memory before the processor needs them. This preliminary action ensures that battery state information is captured and preserved even when the processor is occupied with other tasks like communication protocols, preventing any loss of critical measurement data.
4Use of energy by moving object
If the measurement system enters a lower power consumption state to reduce energy usage, then power efficiency is improved, but the ability to perform synchronous voltage and current measurements is reduced
Solution Approach 1:
The measurement system operates in periodic cycles, alternating between low-power sleep mode and active measurement mode. During sleep mode, only essential monitoring continues with minimal power consumption. When measurement conditions require synchronous voltage and current measurements, the system periodically activates the full measurement capability, achieving both power efficiency and measurement precision through time-based operation patterns.
Data Source
AI summary
Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.


