Synchronous Clock Distribution Circuit for Blade Processor Time Alignment
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Solution Overview
Problem
High-performance computer systems face issues when all processors do not have an identical notion of current time or when their time advancement rates differ, leading to problems such as inconsistent time stamps and potential data order errors in distributed applications.
Innovation Solution
A computer system is designed with a clock signal distribution circuit that generates processor clock signals of the same frequency for all processors, using a synchronous communication network to synchronize clock signals across multiple printed circuit boards, ensuring all processors operate at the same frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If each processor uses its own independent clock signal source, then device complexity is reduced and ease of manufacture is improved, but time synchronization precision deteriorates and manufacturing precision of time advancement rates worsens
Solution Approach 1:
The patent introduces an intermediary clock signal distribution network that carries a reference clock signal from a central source to all processors. This intermediary mechanism ensures that all processors receive the same reference clock signal with identical frequency and phase, thereby achieving precise time synchronization without requiring complex individual clock sources at each processor. The intermediary distribution network resolves the contradiction by providing a simple yet effective method to maintain manufacturing ease while ensuring precise time advancement rates across all processors.
2Manufacturing precision
If a centralized clock signal distribution system is used, then time synchronization precision is improved, but device complexity increases and ease of manufacture deteriorates
Solution Approach 1:
The patent employs a universal clock signal distribution infrastructure that serves multiple functions: it provides time synchronization for all processors, establishes a common time reference for the entire system, and enables coordinated operation across distributed components. This multi-functional approach reduces device complexity by consolidating what could be multiple separate synchronization mechanisms into a single unified clock distribution system, thereby achieving precise time synchronization without proportionally increasing complexity.
3Adaptability or versatility
If processors operate with different clock frequencies, then adaptability to different processing requirements is improved, but time synchronization precision deteriorates
Solution Approach 1:
The patent implements a dynamic clock frequency configuration system where processors can operate at different frequencies based on their specific processing requirements while maintaining time synchronization. The system dynamically adjusts individual processor clock frequencies relative to the common reference clock, allowing each processor to be optimized for its workload while the centralized distribution ensures that all processors maintain a precise relationship between their time advancements. This dynamic approach resolves the contradiction by enabling frequency adaptability without sacrificing time synchronization precision.
Data Source
AI summary
Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.