Synchronous Clock Generator Circuit for Multiphase DC-DC Converters
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Solution Overview
Problem
Current synchronous clock generator circuits for multiphase DC-DC converters face challenges in maintaining stable clock period and balanced phase shift, especially when the number of phases changes dynamically, due to complex circuit implementations and high error rates associated with ring oscillator and phase-lock-loop technologies.
Innovation Solution
A novel synchronous clock generator circuit comprising a front-end buffer, ramp signal generator, voltage reference generator, comparators, pulse generators, and pulse combination circuit, which generates a stable synchronous loop frequency independent of phase number changes, and distinguishes master and slave clock signals by pulse width without additional identification signals, simplifying circuit layout and reducing pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a ring oscillator circuit is used to directly convert the original clock signal to a new clock signal at N times of fsw, then the circuit implementation is simple, but it needs an additional circuit to identify the master clock and slave clock, and large errors occur when the switching frequency or phase number increases
Solution Approach 1:
The patent segments the clock generation function into multiple independent modules: ring oscillator for frequency multiplication, phase detector for master clock identification, and phase shift register for precise phase control. This segmentation allows each module to be optimized independently, reducing overall complexity while maintaining high precision.
Solution Approach 2:
The patent introduces a phase detector as an intermediary component between the ring oscillator and the output stages. This intermediary identifies the master clock by detecting the original clock signal's rising edge and generates control signals to synchronize the N-phase outputs, eliminating the need for additional master/slave identification circuits while maintaining frequency accuracy.
2Reliability
If a phase-lock-loop (PLL) circuit is used to generate the clock signal at N times of fsw, then the clock signal stability is improved, but the circuit implementation becomes complex and large errors occur during phase number changes due to control-loop bandwidth and delay
Solution Approach 1:
The patent extracts the essential function of the PLL (frequency multiplication and phase synchronization) and implements it using simpler components: a ring oscillator for frequency multiplication, a phase detector for synchronization, and a phase shift register for phase distribution. This extraction eliminates the complex feedback control loop of traditional PLL while achieving similar stability with reduced circuit complexity and faster response to phase number changes.
Solution Approach 2:
The patent implements dynamic phase number adaptation by using a phase shift register that can be reconfigured in real-time. When the phase number changes, the system dynamically adjusts the number of active phases without requiring PLL relocking, eliminating settling time errors and achieving instant adaptation to new operating conditions.
3Measurement precision
If additional circuits are added to identify master and slave clock signals, then the clock signal distribution accuracy is improved, but the pin count and circuit layout complexity increase
Solution Approach 1:
The phase detector serves multiple functions simultaneously: it identifies the master clock by detecting the original clock signal, generates the synchronized N-phase clock signals, and provides the reference for the phase shift register. This multi-functionality eliminates the need for separate master/slave identification circuits, reducing pin count and layout complexity while maintaining distribution accuracy.
Solution Approach 2:
The patent merges the master clock identification function with the clock signal generation function in the phase detector. By combining these functions into a single integrated circuit block, the system eliminates additional identification circuits and reduces the number of external pins required, simplifying both the circuit layout and overall system architecture.
Data Source
AI summary
This present invention is an invented synchronous clock generator for the multiphase DC-DC converter system, comprising a front-end buffer circuit, a ramp signal generator circuit, a configurable equally divided reference voltage generator circuit, a set of comparators, a 10-ns pulse generator, multiple 30-ns pulse generators, and a pulse combination circuit. The synchronous clock generator can produce a clock pulse signal SYNC at N (total phase number) times the single-phase switching frequency. Within one synchronous loop period, a 10-ns pulse is first generated and followed by N-1 30-ns pulses. The master power stage chip detects the 10-ns pulse, and all the slave power stages detect and count the 30-ns pulses to determine when to set their output signal PWM. Thus, the invention can produce the new SYNC signal immediately with balanced phase shift while allowing the changing of the total phase number N by the total phase number register.