Synchronous Clock Multiplexing for Glitch-Free Output Enable
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Solution Overview
Problem
Existing digital circuits face issues with asynchronous clock multiplexing and output-enable operations, leading to undesired glitches due to asynchronous changes in select and enable signals, which can cause malfunction in digital circuits.
Innovation Solution
A synchronous circuit design using phase-locked loop (PLL), three-input AND gates, flip-flops, and an OR gate to synchronize clock multiplexing and output-enable operations, ensuring that changes occur only at active edges of the clock signals, and additional enhancements with delay-buffers and XNOR gates to prevent glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If asynchronous clock multiplexing and output-enable operations are used, then circuit complexity is reduced, but glitches occur in the output signal
Solution Approach 1:
The patent applies preliminary action by synchronizing the select signal and enable signal to the clock edge before they control the multiplexer and output enable functions. This ensures that all control signals are aligned to the same time reference (clock edge) before affecting the output, preventing asynchronous transitions that cause glitches while maintaining relatively simple circuit architecture.
2Reliability
If synchronous operation with clock edge alignment is implemented, then glitch-free output is achieved, but circuit complexity increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a clock edge detection mechanism that mediates between the control signals (select, enable) and the multiplexer/output enable functions. This intermediary synchronization layer ensures all control signals are aligned to clock edges before execution, achieving glitch-free operation without requiring complete redesign of the entire circuit architecture.
3Reliability
If multiple logic gates and synchronization components are added, then glitches are prevented, but power consumption increases
Solution Approach 1:
The patent performs synchronization of control signals to clock edges as a preliminary action before the multiplexer and output enable operations. By aligning all control signals in advance to the same clock reference, the circuit avoids the need for additional glitch-prevention components during operation, thereby reducing continuous power consumption while maintaining reliable glitch-free output.
Data Source
AI summary
A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.