Synchronous Clock Rate Change Without Extra Hardware
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Solution Overview
Problem
Conventional systems face challenges in achieving maximum power savings during low activity or low power states as they require additional hardware for synchronous clock rate changes, which is not scalable and efficient across multiple processor cores and DMA clients.
Innovation Solution
A method for synchronously changing the clock rate in a system without additional hardware, where a primary processor core coordinates the clock rate change by informing and synchronizing other processor cores and DMA clients to stop and resume access to shared DRAM, enabling scalable power management across multiple processor cores and DMA clients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional hardware is used to assist in synchronous clock rate changes, then the reliability of clock rate transition is improved, but the device complexity and cost increase
Solution Approach 1:
The system uses existing processor cores and DMA clients to actively participate in the clock rate change process by suspending and resuming memory access. The hardware resources already present in the system serve the additional function of synchronizing clock rate transitions, eliminating the need for dedicated synchronization hardware.
Solution Approach 2:
Existing hardware components (processor cores, DMA clients, memory subsystem) are made multi-functional by requiring them to both perform their primary computational/Data transfer roles and simultaneously participate in clock rate synchronization by controlling their memory access patterns. This eliminates dedicated synchronization hardware.
2Adaptability or versatility
If the system supports multiple processor cores and DMA clients, then the adaptability and scalability are improved, but coordinating clock rate changes becomes more complex
Solution Approach 1:
Before the clock rate change occurs, the system issues suspend commands to all processor cores and DMA clients, ensuring they are ready to stop memory access. This preliminary coordination ensures that when the clock rate changes, all components are already in the correct state, simplifying the transition process even in multi-core systems.
Solution Approach 2:
The system uses a feedback mechanism where processor cores and DMA clients signal when they have suspended and resumed memory access. This allows the initiating core to track the state of all system components and coordinate the clock rate change process, ensuring proper synchronization across multiple cores and DMA clients.
3Ease of operation
If the clock rate is changed asynchronously, then the ease of operation is improved, but the power savings are reduced due to incomplete synchronization
Solution Approach 1:
The system dynamically adjusts the clock rate based on system state while maintaining synchronization through coordinated memory access suspension. The clock rate change is performed in a dynamic manner that adapts to the current operational state of processor cores and DMA clients, achieving both energy efficiency and operational flexibility.
Data Source
AI summary
A system includes a shared memory and a plurality of processor cores communicatively coupled to the shared memory. The system includes a processor core memory and a clock subsystem for providing a clock signal to the shared memory and the plurality of processor cores. Each of the plurality of processor cores executes instructions stored in the processor core memory for synchronously changing the clock rate provided by the clock subsystem to the plurality of processor cores.