Synchronous Data Processing System Clock Inversion Feedback
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Solution Overview
Problem
Synchronous data processing systems face challenges in reliable data transfer due to increasing phase skew caused by propagation delay and PVT variations, which conventional PLL circuits cannot effectively compensate for when propagation delay exceeds one clock cycle, leading to incorrect data sampling.
Innovation Solution
A synchronous data processing system that includes a memory controller with a clock inverter to transmit an inverted clock signal and an asynchronous FIFO buffer to align clock and data signals, ensuring consistent phase delay and improving data sampling by using a feedback mechanism to route the memory clock signal for accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of busses connecting processors and peripherals is increased to improve system performance, then data transfer speed is improved, but phase skew between clock and data signals increases due to propagation delay and PVT variations, leading to incorrect data sampling
Solution Approach 1:
The patent inverts the conventional approach by having the memory module (rather than the memory controller) generate the clock signal used for data sampling. The memory module loops back the input clock signal, inverts its phase using a D-type flip-flop, and uses this inverted clock to sample incoming data. This inversion of the clock generation role resolves the phase skew problem by ensuring the sampling clock experiences the same propagation delays as the data signals.
Solution Approach 2:
The patent implements a feedback mechanism where the memory module receives the input clock signal from the memory controller, processes it through a D-type flip-flop to generate an inverted clock signal, and feeds this processed clock signal back to the memory controller for data sampling. This feedback loop ensures that the sampling clock is synchronized with the actual data arrival time, compensating for propagation delays and PVT variations.
2Reliability
If a PLL circuit is employed to compensate for phase skew between clock and data signals, then data sampling is improved, but the solution is limited to cases where propagation delay is less than one clock cycle and occupies significant circuit board area
Solution Approach 1:
The patent extracts the clock signal processing function from the memory controller and relocates it to the memory module. By taking out the clock inversion and generation logic from the conventional PLL location (memory controller) and placing it in the memory module, the patent eliminates the need for complex PLL circuits while achieving the same phase alignment goal with simpler hardware.
Solution Approach 2:
The patent creates a copy of the input clock signal at the memory module, processes this copied signal through a D-type flip-flop to generate the inverted clock, and uses this copied and processed clock for data sampling. This copying approach allows the system to maintain the original clock signal for other functions while generating a specialized sampling clock with the appropriate phase characteristics.
Data Source
AI summary
A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.