Synchronous Digital Circuit Function Call Hardware Instance
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Solution Overview
Problem
Hardware description languages (HDLs) require extensive code for modeling digital logic circuits, leading to inefficiencies and errors, especially when converted from C-language code, resulting in poor hardware resource utilization and performance.
Innovation Solution
A multi-threaded imperative programming language is used to generate a synchronous digital circuit (SDC) with a single hardware instance for function calls from multiple locations, implemented using hardware pipelines and queues, optimizing hardware utilization in FPGAs and other devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If C to HDL tools are used to convert C-language code into HDLs, then code conversion is achieved, but hardware resources are inefficiently utilized due to creation of multiple instances of the same hardware
Solution Approach 1:
The patent implements a universal hardware instance that can be dynamically reused across multiple function call locations through a single-instance architecture. The hardware is designed to be called from multiple locations in the program source code, allowing one hardware instance to serve multiple purposes and locations, thereby reducing the total quantity of hardware resources needed while maintaining full functionality.
2Adaptability or versatility
If multiple instances of the same hardware are created for function calls from multiple locations, then all function calls are supported, but hardware resource utilization becomes inefficient
Solution Approach 1:
The patent merges multiple potential hardware instances into a single shared hardware instance. By combining the functionality that would otherwise require separate hardware instances at different call locations into one unified instance, the system achieves efficient resource utilization while maintaining the ability to serve multiple function call locations through dynamic allocation and control mechanisms.
3Reliability
If HDLs are used to model digital logic circuits, then circuit functionality is achieved, but the number of lines of code increases significantly leading to more errors and poor performance
Solution Approach 1:
The patent uses a high-level programming language with constructs that can be directly compiled to hardware, avoiding the need for extensive HDL code. By copying the simplicity and readability of high-level programming syntax into the hardware description framework, the system reduces the number of lines of code required while maintaining circuit functionality and reducing errors associated with complex HDL modeling.
Data Source
AI summary
A multi-threaded imperative programming language includes a language construct defining a function call. A circuit implementation for the construct includes a first pipeline, a second pipeline, and a third pipeline. The first hardware pipeline outputs variables to a first queue and outputs parameters for the function to a second queue. The second hardware pipeline obtains the function parameters from the second queue, performs the function, and stores the results of the function in a third queue. The third hardware pipeline retrieves the results generated by the second pipeline from the second queue and retrieves the variables from the first queue. The third hardware pipeline performs hardware operations specified by the source code using the variables and the results of the function. A single instance of the circuit implementation can be utilized to implement calls to the same function made from multiple locations within source code.