Mapping Software Constructs to Deadlock-Free Synchronous Digital Circuits
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Solution Overview
Problem
Hardware Description Languages (HDLs) require extensive code for modeling digital logic circuits, leading to time-consuming design processes and a high likelihood of errors, especially for software engineers unfamiliar with HDLs, and can result in poor performance or deadlocks in electronic circuits.
Innovation Solution
A multi-threaded imperative programming language is used to generate synchronous digital circuits, reducing code requirements and eliminating common design errors by mapping programming constructs directly to circuit implementations, ensuring thread ordering and preventing deadlocks through queue capacity management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If HDLs are used to model digital logic circuits, then the circuits can be designed and implemented, but the number of lines of code becomes extremely large and the design process becomes extremely time consuming
Solution Approach 1:
The patent uses C code as a template or copy that can be directly translated into HDL code through automated code generation tools. This allows software engineers to write code in a familiar language and automatically generate the corresponding hardware description, dramatically reducing design time and code complexity while maintaining the same functional behavior.
Solution Approach 2:
The patent introduces code generation tools and translation mechanisms as intermediaries between C code and HDL code. These tools automatically convert high-level C descriptions into detailed HDL implementations, eliminating the need for engineers to manually write complex HDL code and reducing both design time and error rates.
2Adaptability or versatility
If more lines of code are present in an HDL design, then more functionality can be implemented, but the likelihood of errors increases
Solution Approach 1:
By copying proven C code patterns and algorithms into hardware designs through automated generation, the patent reduces errors associated with manual HDL coding. The automated translation process ensures consistency and correctness, maintaining high functionality while minimizing human-introduced errors.
Solution Approach 2:
The code generation system performs self-validation and error checking during the translation process from C to HDL. The automated tools can detect and correct issues before synthesis, reducing the error rate without requiring additional manual verification steps.
3Adaptability or versatility
If HDLs are used by software engineers unfamiliar with the language, then circuit design can be attempted, but the resulting circuits often include errors or perform poorly
Solution Approach 1:
Software engineers can copy their existing C code into the design flow and automatically generate HDL implementations. This eliminates the need for software engineers to learn HDL syntax and paradigms, allowing them to leverage their existing programming skills while maintaining high circuit performance through automated, optimized code generation.
Solution Approach 2:
The code generation tools serve as an intermediary that translates software engineers' C code into optimized HDL implementations. This mediator handles the complexity of hardware-specific optimizations and best practices, allowing software engineers to achieve high-performance designs without becoming experts in HDL.
4Productivity
If conventional HDL-based solutions are used, then digital logic circuits can be modeled, but the design process becomes extremely time consuming
Solution Approach 1:
The patent enables copying of C code directly into hardware design projects, with automated tools generating the corresponding HDL code. This approach can reduce design time by a factor of 10 or more compared to manual HDL coding, as engineers write code once in C and automatically generate the hardware implementation without repetitive manual translation.
Data Source
AI summary
A language disclosed herein includes a loop construct that maps to a circuit implementation. The circuit implementation may be used to design or program a synchronous digital circuit. The circuit implementation includes a hardware pipeline that implements a body of a loop and a condition associated with the loop. The circuit implementation also includes the hardware first-in-first-out (FIFO) queues that marshal threads (i.e. collections of local variables) into, around, and out of the hardware pipeline. A pipeline policy circuit limits a number of threads allowed within the hardware pipeline to a capacity of the hardware FIFO queues.