Synchronous DRAM Refresh Mechanism for High-Density Memory
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Solution Overview
Problem
As memory cell density increases in dynamic semiconductor memories, the need arises for improved refresh mechanisms that address power requirements without sacrificing time available for normal read/write operations, as current multi-bank, time division approaches to refreshing DRAMs lead to increased power consumption and reduced performance due to longer refresh times and larger number of refresh operations.
Innovation Solution
A synchronous dynamic memory circuit that employs a hidden refresh mode allowing simultaneous read/write and refresh operations within the same memory bank, using a flag to indicate refresh mode and an address comparator to resolve address conflicts, thereby canceling refresh operations and suppressing internal pre-charge pulses to enable continuous access during refresh cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bank, time division refresh approach is used, then power consumption is reduced and performance is maintained, but as memory cell density increases, refresh time must be increased or number of refresh operations must be increased, leading to increased power consumption and reduced performance
Solution Approach 1:
The patent merges the refresh operation with normal read/write operations by allowing them to occur simultaneously in the same memory bank. The refresh operation is initiated by a refresh command while normal access operations can proceed concurrently, eliminating the need to separate these operations in time or space. This merging approach allows the memory system to perform refresh without dedicating separate time slots or banks, thereby reducing the overall number of refresh operations needed and lowering power consumption even as density increases.
Solution Approach 2:
The memory bank is designed to perform multiple functions simultaneously: it can perform both refresh operations and normal read/write operations at the same time. The same memory bank that normally handles data access is also capable of performing refresh operations without requiring separate dedicated refresh banks. This multi-functionality allows the system to maintain performance while handling increased density, as the universal bank can serve dual purposes without conflict.
2Reliability
If multi-bank, time division refresh approach is used, then normal read/write operations can proceed, but refresh operations cause all data accesses to stall, adversely impacting performance
Solution Approach 1:
The patent combines refresh operations with normal access operations in the same time period and same memory bank. Instead of stalling data accesses during refresh, the system allows both operations to proceed concurrently. The refresh command initiates a refresh sequence while normal read/write operations continue uninterrupted, effectively merging these previously separate functions into a unified operation that maintains both data retention and performance.
Solution Approach 2:
The patent introduces an address comparator as an intermediary component that monitors both refresh addresses and normal access addresses. When a conflict is detected (same address being accessed for both refresh and normal operation), the comparator generates a signal to cancel the refresh operation at that specific location, allowing the normal access to proceed. This intermediary mechanism resolves conflicts without requiring complete refresh stalls, thereby maintaining performance while ensuring data retention.
3Duration of action of stationary object
If refresh operations are performed periodically every tREFI, then data retention is maintained, but the time required for refresh operations (tRFC) reduces the time available for normal read/write operations
Solution Approach 1:
The patent merges the time periods for refresh operations and normal read/write operations into a single concurrent execution model. Instead of allocating separate time slots where refresh occurs at the expense of normal operations, both operations are allowed to proceed simultaneously within the same time framework. This eliminates the time loss associated with sequential execution while maintaining the required data retention period through concurrent refresh activities.
Solution Approach 2:
The patent enables continuous useful action by allowing normal read/write operations to proceed without interruption during refresh cycles. The refresh operation does not create gaps or stalls in the normal data access flow; instead, both operations continue continuously and concurrently. This continuity maximizes the time available for productive normal operations while still maintaining data retention through ongoing refresh activities.
4Quantity of substance
If higher density memory cells are refreshed simultaneously every tREFI, then all memory cells are refreshed, but the number of cells refreshed simultaneously increases, presenting a heavy power load
Solution Approach 1:
The patent merges refresh operations with normal access operations so that not all memory cells need to be refreshed simultaneously. By allowing concurrent execution, the system can refresh cells on-demand or in smaller batches while normal operations continue, distributing the power load over time rather than concentrating it in a single simultaneous refresh event. This reduces the peak power load while still refreshing all necessary cells.
Data Source
AI summary
Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at the same time as normal access for read/write operation. In a specific embodiment, to resolve conflicts between addresses, an address comparator compares the address for normal access to the address for refresh operation. In case of a match between the two addresses, the invention cancels the refresh operation at that array and allows the normal access to proceed.