Synchronous Exception Mechanism for Accurate Processor State Capture

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Solution Overview

Problem

Existing program execution monitoring techniques face challenges in accurately capturing the state of a system at the time of interest due to asynchronous exceptions, which can result in a mismatch between the state at the time of exception handling and the state at the time of the interesting instruction execution.

Innovation Solution

The implementation of a synchronous exception mechanism, where a further instruction in the sequence is marked with a synchronous exception, causing the processing pipeline to trigger an exception handling routine instead of executing it, thereby allowing for the collection of state information at a deterministic point close to the interesting instruction's execution time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If asynchronous exception is used to monitor program execution, then program execution can be monitored, but the state information collected does not accurately reflect the system state at the time of the interesting instruction

Engineering Contradiction:
Improveaccuracy of state informationVSAvoidtime delay between instruction execution and exception handling
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-identifying interesting instructions and pre-determining the timing of synchronous exceptions. The exception timing is calculated in advance based on instruction latency and pipeline depth, ensuring that when the synchronous exception occurs, the state information collected accurately reflects the system state at the time of the interesting instruction execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the timing parameter of exception handling from asynchronous (indeterminate timing) to synchronous (deterministic timing). By controlling when the synchronous exception occurs relative to the interesting instruction, the system achieves accurate correlation between the instruction execution and state information collection without the time loss inherent in asynchronous approaches.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If synchronous exception is triggered on the interesting instruction itself, then state information can be collected at the correct time, but the interesting instruction execution is interfered with

Engineering Contradiction:
Improveaccuracy of state informationVSAvoidinstruction execution integrity
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent segments the exception triggering into two separate components: the interesting instruction that executes normally and a subsequent instruction that triggers the synchronous exception. This segmentation allows the interesting instruction to complete its execution undisturbed while still enabling state information collection at the precise moment needed, thus maintaining both measurement precision and execution integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary instruction between the interesting instruction and the exception handling routine. This intermediary instruction serves as a mediator that, when executed, triggers the synchronous exception. It allows the system to collect state information at the correct time without directly interrupting the interesting instruction, thereby preserving execution integrity while achieving accurate measurement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12045154B2Technique for collecting state information of an apparatus
Publication Date: 2024.07.23 ARM LTD
  • US12045154B2 patent drawing
  • US12045154B2 patent drawing
  • US12045154B2 patent drawing

AI summary

A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.