Synchronous Flash Programming Across Modules to Reduce Latency

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Solution Overview

Problem

Conventional flash-based memory systems experience performance inefficiencies due to increasing latency as block sizes grow, affecting the efficiency of data operations across multiple memory modules.

Innovation Solution

A method for synchronously programming multiple memory modules by sending instructions for first and second data operations, waiting for their completion, and validating data across modules, which reduces latency without negatively impacting system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If block sizes in flash memory continue to increase, then storage capacity is improved, but latency involved with performing each flash operation increases

Engineering Contradiction:
Improvestorage capacityVSAvoidoperation latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent divides the programming operation into multiple smaller voltage ramping stages rather than applying the full voltage change in a single step. This segmentation of the programming process into incremental steps reduces the time required for each operation while maintaining the ability to program larger memory blocks, thereby resolving the contradiction between storage capacity and operation latency.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If conventional programming methods are used on multiple memory modules, then system simplicity is maintained, but operating efficiency decreases due to increased latency

Engineering Contradiction:
Improvesystem simplicityVSAvoidoperating efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements continuous voltage ramping across multiple memory modules simultaneously, maintaining uninterrupted programming action throughout the process. This continuous operation eliminates idle waiting periods between operations on different modules, significantly improving productivity while keeping the system architecture relatively simple through parallel processing.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system performs preliminary voltage ramping steps before the final programming voltage is applied to all memory modules. This preliminary action prepares the memory cells in advance, allowing the subsequent full programming operation to complete more quickly, thereby enhancing operating efficiency without substantially increasing system complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12379846B2Synchronously programming multiple memory devices
Publication Date: 2025.08.05 QUANTA COMPUTER INC
  • US12379846B2 patent drawing
  • US12379846B2 patent drawing
  • US12379846B2 patent drawing

AI summary

An example computer-implemented method for synchronously programming multiple memory modules includes sending one or more instructions to each of the memory modules to perform a first data operation associated with a computer software update. In response to determining that each of the memory modules have received the first instructions to perform the first data operation, time is spent waiting for the first data operation to be completed at each of the memory modules. One or more instructions are also sent to each of the memory modules to perform a second data operation associated with the computer software update. In response to determining that each of the memory modules have received the second instructions to perform the second data operation, time is spent waiting for the second data operation to be completed at each of the memory modules. Furthermore, the data is validated across the memory modules.