Synchronous Hardware Timestamping via External PHY Switching
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Solution Overview
Problem
Current technologies face challenges in providing hardware-based support for precision timestamping and synchronization under the IEEE 1588 standard, particularly due to limited options for switching ICs, PHY components, and high costs of FPGA solutions, with a lack of support for both gigabit and fast Ethernet interfaces at compact form factors.
Innovation Solution
The solution involves a data packet switching apparatus with a primary gigabit Ethernet switch connected to multiple secondary fast Ethernet switches, utilizing external dedicated PHY devices for timestamping and synchronization, allowing for precision timestamping across a higher port count and supporting disparate switches from different suppliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a primary gigabit Ethernet switch is connected to multiple secondary fast Ethernet switches with external dedicated PHY devices, then the port count and support for both gigabit and fast Ethernet interfaces is improved, but the device complexity increases
Solution Approach 1:
The system is divided into a primary gigabit Ethernet switch and multiple secondary fast Ethernet switches, each with external dedicated PHY devices. This segmentation allows the system to support both gigabit and fast Ethernet interfaces while distributing the complexity across multiple independent components rather than requiring a single complex integrated solution.
Solution Approach 2:
The primary gigabit Ethernet switch serves multiple functions: it acts as a timestamping reference for both gigabit and fast Ethernet interfaces, and it connects to multiple secondary switches to provide both gigabit and fast Ethernet port support. This multi-functionality reduces the need for separate dedicated hardware for each interface type.
2Measurement precision
If external dedicated PHY devices are used for timestamping, then the precision timestamping accuracy is improved, but the manufacturing cost increases
Solution Approach 1:
External dedicated PHY devices serve as intermediaries between the primary gigabit Ethernet switch and the secondary fast Ethernet switches. These PHY devices perform the precise timestamping function, allowing the primary switch to maintain accuracy while the secondary switches can be implemented at lower cost with standard components.
Solution Approach 2:
The system uses standard, off-the-shelf PHY devices rather than custom expensive FPGA solutions. While individual PHY devices have cost, using multiple standardized components is more economical than developing and manufacturing custom high-precision timestamping hardware for each interface.
3Reliability
If hardware-based support for IEEE 1588 is implemented, then the synchronization accuracy is improved, but the device complexity increases
Solution Approach 1:
The hardware-based IEEE 1588 timestamping functionality is extracted and concentrated in the primary gigabit Ethernet switch and external dedicated PHY devices, while the secondary fast Ethernet switches implement standard Ethernet functionality. This extraction allows high synchronization accuracy where needed without requiring all components to be complex.
Solution Approach 2:
High-precision hardware timestamping is implemented locally at the primary gigabit Ethernet switch and external PHY devices, while secondary fast Ethernet switches use standard, simpler Ethernet controllers. This localized approach provides IEEE 1588 compliance where required without unnecessarily complicating the entire system.
Data Source
AI summary
Methods and apparatus that may be used to provide timestamps to physical layer devices are provided. One method includes obtaining a time value from a clock associated with a physical layer device that is communicatively coupled to a primary data packet switch. The method further includes adding a processing time to the time value to generate a timestamp and transmitting the timestamp to a multiplexer circuit. The method further includes writing the timestamp in parallel from the multiplexer circuit to a plurality of external physical layer devices that are communicatively coupled to a secondary data packet switch and are located external to a housing of the secondary data packet switch.