Synchronous Hierarchical Circuit Design Timing Closure
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Solution Overview
Problem
The challenge in electronic circuit design is the difficulty in achieving timing closure due to increasing complexity and shrinking feature sizes, which leads to significant timing delays and susceptibility to breakdowns, particularly in deep-submicron regimes, where conventional methods fail to efficiently manage wire lengths and interconnect materials, resulting in costly reassembly iterations and potential timing degradation.
Innovation Solution
A method for synchronous hierarchical implementation of electronic circuit designs that synchronizes block and top-level implementations using connectivity information and system intelligence layers, allowing for parallel processing and budgeting adjustments across hierarchical levels to reduce reassembly iterations and optimize timing without resorting to costly reassembly cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to manage wire lengths and interconnect materials in deep-submicron regimes, then manufacturing processes can be simplified, but timing closure becomes difficult to achieve and timing delays increase significantly
Solution Approach 1:
The patent divides the hierarchical electronic design into multiple levels (block level and chip level) and processes timing constraints at each level independently before integrating them. This segmentation allows timing closure to be achieved at the block level without waiting for complete chip-level routing, thereby maintaining manufacturing simplicity while improving timing closure accuracy.
Solution Approach 2:
The patent performs timing constraint propagation and budgeting before the actual routing and placement processes. By establishing timing budgets at the block level in advance and propagating them to lower hierarchical levels, the system prepares timing information ahead of time, enabling timing closure to be maintained even as feature sizes shrink and manufacturing becomes more complex.
2Speed
If feature sizes are shrunk to meet device performance goals, then device speed and functionality improve, but timing delays from wires become more significant and manufacturing complexity increases
Solution Approach 1:
The patent segments the timing analysis and constraint propagation into hierarchical levels, allowing timing budgets to be established at the block level before chip-level routing. This enables the system to manage timing delays from shrinking wires by processing constraints at appropriate hierarchical levels, maintaining device speed improvements while managing manufacturing complexity through structured constraint propagation.
Solution Approach 2:
The patent changes the parameter of timing constraint propagation by distributing timing budgets from higher hierarchical levels to lower levels based on connectivity information. This parameter change allows the system to adapt timing requirements to the specific structure of each block, enabling feature size reduction for speed improvement while managing the increased manufacturing complexity through intelligent parameter distribution.
3Productivity
If independent block implementation is performed without synchronization, then implementation efficiency improves, but reassembly iterations increase and timing closure becomes problematic
Solution Approach 1:
The patent implements feedback by propagating timing budget information from the top level back to lower hierarchical levels. Block-level timing budgets are calculated based on chip-level timing constraints and connectivity information, then fed back to guide the implementation at lower levels. This feedback mechanism allows blocks to be implemented efficiently while reducing reassembly iterations, as timing information is already optimized before final assembly.
Solution Approach 2:
The patent performs preliminary timing budget calculation and propagation before the actual block implementation. By establishing timing budgets at higher hierarchical levels in advance and propagating them to lower levels, the system prepares all necessary timing information beforehand. This preliminary action enables blocks to be implemented in parallel without requiring extensive reassembly iterations, thereby maintaining high productivity while minimizing time loss.
4Manufacturing precision
If larger gates with bigger transistors are used to charge wire capacitance, then timing correctness can be maintained, but power consumption and timing delay increase
Solution Approach 1:
The patent changes the parameter of timing constraint propagation by distributing timing budgets based on connectivity information and hierarchical levels. Instead of uniformly increasing gate sizes to charge wire capacitance, the system propagates timing budgets that account for specific wire lengths and capacitance at each hierarchical level. This allows timing correctness to be maintained through intelligent budget distribution rather than excessive gate sizing, thereby reducing power consumption.
Solution Approach 2:
The patent applies local quality by tailoring timing budgets to specific blocks and their connectivity characteristics. Rather than using uniform large gates throughout, the system calculates and propagates timing budgets that are specific to each block's wire length, capacitance, and hierarchical level. This local customization allows timing correctness to be achieved with appropriate local adjustments rather than global over-design, reducing overall power consumption while maintaining timing accuracy.
Data Source
AI summary
Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.