Synchronous Memory Node Switching Without Clock Data Recovery
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Solution Overview
Problem
Existing distributed memory systems face high and unpredictable latencies due to clock data recovery (CDR) processes, which increase energy consumption and latency variability, especially in large memory pools.
Innovation Solution
Implementing a synchronous clock source to synchronize memory nodes within a memory pool, eliminating the need for clock data recovery by using a synchronized clock signal for encoding and decoding memory data across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock data recovery (CDR) is used in distributed memory nodes, then each node can independently handle clock signals, but latency increases and becomes unpredictable
Solution Approach 1:
The patent merges the clock signal distribution function into a centralized clock source that serves multiple memory nodes simultaneously. Instead of each node performing independent CDR, a single synchronized clock signal is distributed to all nodes, eliminating redundant clock recovery operations and reducing latency while maintaining reliable clock synchronization across the memory pool.
2Reliability
If clock data recovery (CDR) is performed at each memory node, then nodes can operate independently, but energy consumption increases
Solution Approach 1:
The patent combines the clock signal generation and distribution function into a centralized clock source that serves multiple memory nodes. This eliminates the need for each node to perform energy-intensive CDR operations independently, significantly reducing total energy consumption while maintaining independent operational capability through the distributed synchronized clock signal.
3Adaptability or versatility
If memory nodes use disparate clock sources, then nodes can operate autonomously, but latency variability increases
Solution Approach 1:
The patent creates equipotential clock conditions across all memory nodes by distributing a single synchronized clock signal from a centralized source. This ensures that all nodes operate on the same time reference, eliminating latency variability caused by disparate clock sources while maintaining autonomous operational capability through the unified clock distribution architecture.
Data Source
AI summary
A system includes: a group of memory resources including a first memory node and a second memory node, the first memory node being connected to the second memory node over a switching fabric; and a synchronous clock source connected to the first memory node and the second memory node, the synchronous clock source to provide a synchronized clock signal to the first memory node and the second memory node to synchronize the first memory node with the second memory node. The first memory node and the second memory node are to encode memory data and decode encoded memory data using the synchronized clock signal.